KR960026575A - Device Separating Method of Semiconductor Device - Google Patents

Device Separating Method of Semiconductor Device Download PDF

Info

Publication number
KR960026575A
KR960026575A KR1019940038571A KR19940038571A KR960026575A KR 960026575 A KR960026575 A KR 960026575A KR 1019940038571 A KR1019940038571 A KR 1019940038571A KR 19940038571 A KR19940038571 A KR 19940038571A KR 960026575 A KR960026575 A KR 960026575A
Authority
KR
South Korea
Prior art keywords
cvd
film
oxide
forming
device isolation
Prior art date
Application number
KR1019940038571A
Other languages
Korean (ko)
Other versions
KR0146626B1 (en
Inventor
권성구
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940038571A priority Critical patent/KR0146626B1/en
Publication of KR960026575A publication Critical patent/KR960026575A/en
Application granted granted Critical
Publication of KR0146626B1 publication Critical patent/KR0146626B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 버즈비크의 발생을 최소화할뿐 아니라 소자분리막의 표면의 평탄화를 이룰 수 있는 반도체 소자의 분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and to a method of forming a separator of a semiconductor device capable of minimizing the occurrence of a buzz beak and planarizing the surface of the device isolation film.

Description

반도체 소자의 소자분리막 형성방법Device Separating Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A 내지 2G도는 본 발명에 따른 소자분리막 형성방법을 설명하기 위한 단면도, 제3A 내지 3D도는 본 발명의 제1실시예를 설명하기 위한 단면도, 제4A 내지 4B도는 본 발명의 제2실시예를 설명하기 위한 단면도.2A through 2G are cross-sectional views illustrating a method of forming an isolation layer in accordance with the present invention, FIGS. 3A through 3D are cross-sectional views illustrating a first embodiment of the present invention, and FIGS. 4A through 4B show a second embodiment of the present invention. Cross section for illustration.

Claims (3)

반도체 소자의 소자분리막 형성방법에 있어서, 실리콘 기판상에 패드 산화막, 제1 CVD 질화막, 제1CVD 산화막, 제2CVD 질화막 및 제2CVD 산화막을 순차로 형성하는 단계와, 상기 제2CVD 산화막 및 제2CVD 질화막을 소정의 폭으로 제거하는 단계와, 노출된 상기 제2CVD 산화막의 측벽에 산화막 스페이서를 형성하는 단계와, 노출된 상기 제1CVD 산화막, 제1CVD 질화막, 패드산화막을 식각한 후 상기 실리콘 기판의 일부를 식각하는 단계와, 잔류하는 상기 제2CVD 산화막 및 상기 산화막 스페이서를 제거하는 단계와, 산화공정을 실시하여 소자분리막을 형성하는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 필드산화막 형성방법.A method of forming a device isolation film of a semiconductor device, the method comprising: sequentially forming a pad oxide film, a first CVD nitride film, a first CVD oxide film, a second CVD nitride film, and a second CVD oxide film on a silicon substrate, and forming the second CVD oxide film and the second CVD nitride film. Removing a predetermined width, forming an oxide spacer on the exposed sidewalls of the second CVD oxide layer, etching the exposed first CVD oxide layer, the first CVD nitride layer, and the pad oxide layer, and then etching a portion of the silicon substrate. And removing the remaining second CVD oxide film and the oxide spacer, and performing an oxidation process to form a device isolation film. 제1항에 있어서, 상기 산화막 스페이서를 형성한 후 직접 산화공정을 실시하여 소자 분리막을 형성하는 것을 특징으로 하는 반도체 소자의 필드산화막 형성방법.The method of forming a field oxide film of a semiconductor device according to claim 1, wherein a device isolation film is formed by performing a direct oxidation process after forming the oxide spacer. 제1항에 있어서, 상기 제2CVD 산화막 및 상기 산화막 스페이서를 제거하는 공정후 전체구조 상부에 CVD 실리콘층을 형성한 다음 산화공정을 실시하여 소자분리막을 형성하는 것을 특징으로 하는 반도체 소자의 소자 분리막 형성방법.2. The device isolation film according to claim 1, wherein after the process of removing the second CVD oxide film and the oxide spacer, a CVD silicon layer is formed on the entire structure, and then an oxide process is performed to form a device isolation film. Way. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038571A 1994-12-29 1994-12-29 Method for forming the separating film of semiconductor device KR0146626B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940038571A KR0146626B1 (en) 1994-12-29 1994-12-29 Method for forming the separating film of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038571A KR0146626B1 (en) 1994-12-29 1994-12-29 Method for forming the separating film of semiconductor device

Publications (2)

Publication Number Publication Date
KR960026575A true KR960026575A (en) 1996-07-22
KR0146626B1 KR0146626B1 (en) 1998-11-02

Family

ID=19404787

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940038571A KR0146626B1 (en) 1994-12-29 1994-12-29 Method for forming the separating film of semiconductor device

Country Status (1)

Country Link
KR (1) KR0146626B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100732797B1 (en) * 2000-12-05 2007-06-27 주식회사 하이닉스반도체 Method for forming a isolation film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100732797B1 (en) * 2000-12-05 2007-06-27 주식회사 하이닉스반도체 Method for forming a isolation film

Also Published As

Publication number Publication date
KR0146626B1 (en) 1998-11-02

Similar Documents

Publication Publication Date Title
KR950021347A (en) Manufacturing Method of Semiconductor Device
KR970030640A (en) Method of forming device isolation film in semiconductor device
KR950010018A (en) A method for manufacturing a semiconductor device including a semiconductor body having a field insulating area formed by a groove filled with an insulating material
KR880009415A (en) Manufacturing Method of Semiconductor Device
KR960026575A (en) Device Separating Method of Semiconductor Device
KR980006074A (en) Field oxide film formation method of a semiconductor device
KR970053429A (en) Device Separation Method of Semiconductor Device
KR960026727A (en) Manufacturing method of high frequency semiconductor device
KR960026610A (en) Field oxide film formation method of semiconductor device
KR950007056A (en) Device isolation oxide film formation method of semiconductor device
KR950001945A (en) Field oxide film formation method
KR940020528A (en) Device Separation Method of Semiconductor Device
KR970023736A (en) Method of forming contact portion of semiconductor device
KR960026571A (en) Device Separating Method of Semiconductor Device
KR950021362A (en) Semiconductor Device Isolation Method
KR970003823A (en) Device Separating Method of Semiconductor Device
KR940016589A (en) Field oxide film manufacturing method
KR950015710A (en) Device Separation Method of Semiconductor Device
KR950021382A (en) Separator Formation Method of Semiconductor Device
KR970053400A (en) Semiconductor device isolation formation method
KR920010824A (en) Device isolation method of semiconductor device
KR920015612A (en) Device isolation method of semiconductor device
KR920013600A (en) Method of forming planar isolation region of semiconductor device
KR970030643A (en) Method of forming device isolation film of semiconductor device
KR970072309A (en) Method of separating semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060502

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee