KR960025747A - Synchronous semiconductor memory device with automatic precharge to ensure minimum last active period - Google Patents

Synchronous semiconductor memory device with automatic precharge to ensure minimum last active period Download PDF

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KR960025747A
KR960025747A KR1019940035783A KR19940035783A KR960025747A KR 960025747 A KR960025747 A KR 960025747A KR 1019940035783 A KR1019940035783 A KR 1019940035783A KR 19940035783 A KR19940035783 A KR 19940035783A KR 960025747 A KR960025747 A KR 960025747A
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signal
generating
open
dress
burst
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KR0142405B1 (en
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김규홍
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김광호
삼성전자 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체메모리장치의 행체인을 자동프리차아지하는 기술분야Technical field to auto precharge the line of semiconductor memory device

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

자동프리차아지 실행 여부를 열어드레스스트로우브 신호가 인가되는 시점, 즉 열어드레스가 선택되는 시점으로 하였으므로 행어드레스스트로우브 신호가 전혀 고려되지 않아서 정의된 최소 라스 액티브구간을 지킬 수 없을 뿐만 아니라 여러개의 뱅크가 있을 때 하나의 뱅크에 대한 자동 프리차아지 명령인가 후 갭없이 다른 뱅크에 대해 자동 프리차아지 명령을인가하면 처음에 인가된 명령이 수행되지 않게 되어 있었으므로 이러한 문제점의 개선을 위함.Since the automatic precharge is executed or not when the open strobe signal is applied, that is, when the open dress is selected, the hang address signal is not considered at all and the defined minimum las active period cannot be maintained. When there is a bank, if an automatic precharge command is applied to another bank after an automatic precharge command for one bank, and an automatic precharge command is applied to another bank without a gap, the first authorized command is not executed.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

행 및 열어드레스스트로우브 신호를 사용하며 다수개의 메모리셀 들을 갖는 다수개의 메모리뱅크 들을 구비하며, 라스신호의 발생시 특정 메모리뱅크가 라스 액티브상태로 되고 그로부터 소정 시간 경과후 특정 메모리뱅크를 자동프리차아지하는 반도체메모리 장치에 있어서, 상기 특정 메모리뱅크의 라스 액티브상태가 최소한으로 보장되도록 하기위한 타이밍제어신호를 발생하는 수단과, 상기 타이밍제어신호에 응답하여 상기 자동프리차아지의 개시를 명하는 신호를 발생하기 위한수단으로 구성되어 자동 프리차아지 기능의 수행시 최소 라스 액티브구간을 보장한다.It is equipped with a plurality of memory banks having a plurality of memory cells using a row and open-dress strobe signal, and when a ras signal is generated, a specific memory bank becomes a las active state, and after a predetermined time has elapsed, a certain memory bank is automatically precharged. A semiconductor memory device, comprising: means for generating a timing control signal for ensuring a least active state of the particular memory bank and a signal for instructing the start of the automatic precharge in response to the timing control signal; It is composed of means for generating to ensure the minimum las active period when performing the automatic precharge function.

4. 발명의 중요한 용도4. Important uses of the invention

반도체메모리장치의 행체인 자동프리차아지 기능의 신뢰성 향상용.For improving the reliability of the automatic precharge function of the semiconductor memory device.

Description

최소 라스 액티브구간을 보장하는 자동 프리차아지기능을 가진 동기식 반도체메모리 장치Synchronous semiconductor memory device with automatic precharge to ensure minimum last active period

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 자동 프라차아지기능을 실현하기 위한 구성들을 보여주는 블럭 다이어그램, 제4도는 제3도중 본 발명에 따른 프리차아지신호 발생회로의 구체적인 구성도, 제5도는 제3도중 본 발명에 따른 버어스트/레이턴시정보신호 발생회로의 구체적인 구성도.Figure 3 is a block diagram showing the configuration for realizing the automatic Pracharge function according to the present invention, Figure 4 is a specific configuration of the precharge signal generating circuit according to the invention of Figure 3, Figure 5 is a view of the A detailed configuration diagram of a burst / latency information signal generation circuit according to the present invention.

Claims (4)

행 및 열어드레스스트로우브신호를 사용하며 다수개의 메모리셀들을 갖는 다수개의 메모리뱅크들을 구비하며, 행어드레스 스트로우브신호의 발생시 특정 메모리뱅크가 라스 액티브상태로 되고 그로 부터 소정 시간 경과 후 특정 메모리뱅크를 자동프리차아지하는 반도체메모리장치에 있어서, 상기 특정 메모리뱅크의 라스 액티브상태가 최소한으로 보장되도록 하기 위한 타이밍제어신호를 발생하는 수단과, 상기 타이밍제어신호에 응답하여 상기 자동프리차아지의 개시를명하는 신호를 발생하기 위한 수단으로 구성됨을 특징으로 하는 최소 라스 액티브구간을 보장하는 자동 프리차아지 기능을 가진 동기식 반도체메모리장치.A plurality of memory banks having a plurality of memory cells using a row and an open-dress strobe signal, and when a row address strobe signal is generated, a specific memory bank becomes las active and a certain memory bank is elapsed after a predetermined time. A semiconductor memory device for automatic precharge, comprising: means for generating a timing control signal for ensuring a las active state of the specific memory bank is minimized, and initiating the automatic precharge in response to the timing control signal; A synchronous semiconductor memory device having an automatic precharge function that guarantees a minimum last active period, characterized in that it is constituted by means for generating a command signal. 행 및 열어드레스스트로우브신호를 사용하며 다수개의 메모리셀들을 갖는 다수개의 메모리뱅크들을 구비하며, 소정의 제어를 받아 특정 메모리뱅크를 자동프리차아지하는 반도체메모리장치에 있어서, 상기 메모리뱅크들 중 하나의 메모리뱅크를 지정하기 위한 신호와, 상기 행어드레스스트로우브신호의 발생에 응답하여 상기 지정된 메모리뱅크의 최소 라스 액티브구간을 설정하기 위한 타이밍신호를 발생하는 수단과, 상기 열어드레스스트로우브신호와 상기 타이밍제어신호의 조합에 응답하여 상기 지정된 메모리뱅크를 자동으로 프리차아지하는 신호를 발생하는 수단을 구비함을 특징으로하는 최소 라스 액티브구간을 보장하는 자동 프리차아지기능을 가진 동기식 반도체메모리장치.12. A semiconductor memory device comprising a plurality of memory banks having a plurality of memory cells, using a row and open address strobe signal, and automatically precharging a specific memory bank under a predetermined control, wherein the memory memory device is one of the memory banks. Means for generating a signal for designating a memory bank of the memory bank; and a timing signal for setting a minimum lath active section of the designated memory bank in response to the generation of the row address strobe signal; And means for generating a signal for automatically precharging the specified memory bank in response to a combination of timing control signals. 다수개의 메모리셀들을 가진 다수개의 메모리뱅크들과, 외부로부터 입력되는 행어드레스스트로우브신호와 뱅크선택신호에 따라 상기 메모리뱅크들 중 하나의 메모리뱅크에 속하는 행관련제어회로들을 구동시키는 행마스터클럭을발생하는 회로와, 외부로부터 열어드레스스트로우브신호를 입력하여 상기 메모리뱅크들중 하나의 메모리뱅크에 속하는 열관련제어회로들을 구동하는 열마스터클럭을 발생하는 회로와, 외부로부터 어드레스신호들을 입력하여 컬럼어드레스신호들을 발생하는 회로를 가지며, 소정의 주파수를 가지는 시스템클럭에 관련된 버어스트길이 및 레이턴시정보에 따라 데이터억세스동작을 수행하는 반도체메모리장치에 있어서, 상기 행마스터클럭에 따르는 타이밍제어신호를 발생하는 수단과, 상기 열마스터클럭과 버어스트길이 및 버어스트길이감지정보로써 상기 버어스트 길이 및 레이턴시정보를 가지는 신호를 발생하기 위한 수단과, 상기 버어스트길이 및 레이턴시정보를 가지는 신호와 상기 타이밍제어신호를 입력하고 소정의 제어신호를 응답하여 상기 열어드레스스트로우브신호와 상기 버어스트길이 및 레이턴시정보를 가지는 정보감지신호를 발생하는 수단과, 상기 열어드레스신호와 상기 열마스터클럭을 입력하여 열어드레스활성감지신호를 발생하여 상기 정보감지신호의 발생을 위한 제어신호로서 제공하며, 상기 열어드레스활성감지신호와 상기 정보감지신호에 응답하는 프리차아지신호를상기 행마스터클럭을 발생하는 회로로 전송하는 수단을 구비함을 특징으로 하는 최소 라스 액티브구간을 보장하는 자동프리차아지기능을 가진 동기식 반도체메모리장치.A row master clock for driving row-related control circuits belonging to one of the memory banks according to a plurality of memory banks having a plurality of memory cells and a row address strobe signal and a bank selection signal input from an external device; A circuit for generating a circuit and a column master clock for driving column-related control circuits belonging to one of the memory banks by inputting an open strobe signal from an external source; A semiconductor memory device having a circuit for generating address signals and performing a data access operation in accordance with burst length and latency information associated with a system clock having a predetermined frequency, comprising: generating a timing control signal according to the row master clock; Sudan, the thermal master clock and the burst road Means for generating a signal having said burst length and latency information as said and burst length detection information, a signal having said burst length and latency information and said timing control signal and responding to a predetermined control signal Means for generating an information detection signal having said open-dress strobe signal and said burst length and latency information, and generating said open-dress activity detection signal by inputting said open-dress signal and said column master clock to generate said open-dress activity detection signal. And a means for transmitting as a control signal for generation, a means for transmitting the open-dress activity detection signal and a precharge signal in response to the information detection signal to a circuit generating the row master clock. Synchronous semiconductor memory device with automatic precharge function to guarantee interval. 행어드레스스트로우브신호를 입력하여 행마스터클럭을 발생하는 버퍼와, 열어드레스스트로우브신호를 입력하여 열관련제어회로들을 구동하는 열마스터클럭을 발생하는 카스버퍼와, 어드레스신호를 입력하여 이 어드레스 신호를씨모오스레벨로 버퍼링하고 또한 버퍼링된 어드레스신호로부터 복수개의 열어드레스신호들을 발생하는 열어드레스발생회로와, 열마스터클럭과 계수된 열어드레스신호들을 입력하여 버어스트길이의 종료상태를 검출하는 버어스트길이 감지신호를 발생하는 버어스트종료감지회로와, 행마스터클럭을 입력하여 타이밍제어신호를 발생하는 타이밍제어회로와, 버어스트길이감지신호와 열마스터클럭을 입력하여 버어스트/레이턴시정보신호를 발생하는 버어스트/레이턴시정보신호 발생회로와, 타이밍제어신호와 버어스트/레이턴시정보신호와 후술할 프리차아지신호발생회로로부터 발생되는 열어드레스활성감지신호를 입력하여 버어스트/레이턴시정보감지신호를 발생하는 버어스트/레이턴시정보감지회로와, 열어드레스신호와 버어스트/레이턴시정보감지신호와 열마스터클럭을 입력하여 프리차아지신호를 발생하여 라스버퍼로 공급하거나 열어드레스활성감지신호를 발생하여 상기 버어스트, 레이턴시 정보를 갖는 신호의 발생을 위한 제어신호로서 제공하는 프리차아지신호발생회로로 구성됨을 특징으로 하는 최소 라스 액티브구간을 보장하는 자동 프리차아지기능을 가진 동기식 반도체메모리장치.A buffer for generating a row master clock by inputting a row address strobe signal, a cas buffer for generating a column master clock for driving column-related control circuits by inputting an open address signal, and an address signal for inputting this address signal Is used to detect the termination state of the burst length by inputting an open-dress generation circuit that buffers the CMOS level and generates a plurality of open-dress signals from the buffered address signal, and a column master clock and the counted open-dress signals. A burst termination detection circuit for generating a length sensing signal, a timing control circuit for generating a timing control signal by inputting a row master clock, and a burst length detection signal and a column master clock are input to generate a burst / latency information signal. Burst / latency information signal generation circuit, timing control signal and burst / Burst / latency information sensing circuit for inputting latency information signal and open-dress activity detection signal generated from a precharge signal generation circuit to be described later to generate a burst / latency information detection signal, and an open-dress signal and a burst / latency A precharge signal is generated by inputting an information detection signal and a thermal master clock to generate a precharge signal and supply it to a las buffer or generate an open dress activity detection signal to provide a control signal for generating a signal having the burst and latency information. A synchronous semiconductor memory device having an automatic precharge function that guarantees a minimum last active period, characterized by comprising an idle signal generating circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940035783A 1994-12-21 1994-12-21 Semiconductor memory device having pre-charge function KR0142405B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100439046B1 (en) * 2001-06-29 2004-07-05 주식회사 하이닉스반도체 Auto precharge circuit in a semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002015570A (en) * 2000-06-28 2002-01-18 Toshiba Corp Semiconductor memory
KR100363480B1 (en) * 2000-07-20 2002-12-05 주식회사 하이닉스반도체 Auto precharge control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100439046B1 (en) * 2001-06-29 2004-07-05 주식회사 하이닉스반도체 Auto precharge circuit in a semiconductor device

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