KR960025707A - Step-up circuits used in active cycles of semiconductor memory devices - Google Patents

Step-up circuits used in active cycles of semiconductor memory devices Download PDF

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Publication number
KR960025707A
KR960025707A KR1019940038503A KR19940038503A KR960025707A KR 960025707 A KR960025707 A KR 960025707A KR 1019940038503 A KR1019940038503 A KR 1019940038503A KR 19940038503 A KR19940038503 A KR 19940038503A KR 960025707 A KR960025707 A KR 960025707A
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KR
South Korea
Prior art keywords
control signal
signal
boosted voltage
circuit
activated
Prior art date
Application number
KR1019940038503A
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Korean (ko)
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KR0137317B1 (en
Inventor
윤세승
박찬종
김병철
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김광호
삼성전자 주식회사
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Priority to KR1019940038503A priority Critical patent/KR0137317B1/en
Priority to TW084113127A priority patent/TW282544B/zh
Priority to DE19547796A priority patent/DE19547796C2/en
Priority to JP7342653A priority patent/JP2828942B2/en
Priority to FR9515663A priority patent/FR2729020B1/en
Priority to CN95120640A priority patent/CN1045838C/en
Priority to GB9526716A priority patent/GB2296593B/en
Publication of KR960025707A publication Critical patent/KR960025707A/en
Application granted granted Critical
Publication of KR0137317B1 publication Critical patent/KR0137317B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Dc-Dc Converters (AREA)

Abstract

본 발명은 반도체 메모리소자의 승압회로에 관한 것으로서, 대기싸이클과 활성싸이클을 결정하는 칩마스터클럭을 입력하여 제1지연기간이 경과한 후에 활성화되며 제1펄스폭을 가진 감지제어신호와 제2지연시간이 경과한 후에 활성화되며 제2펄스폭을 가지는 래치제어신호를 발생하는 제1회로수단과, 상기 감지제어신호와 상기 래치제어신호에 응답하여 현재의 승압전압의 전위상태를 알리는 감지신호를 발생하는 제2회로수단과, 상기 칩마스터클럭에 응답하여 상기 감지신호와 동시에활성화되는 승압전압발생제어신호를 발생하는 제3회로수단과, 상기 감지신호와 상기 승압전압발생제어신호에 따라 상기 대기싸이클 및 활성싸이클에서 각각 동작하는 제1 및 제2승압전압발생회로를 구비한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boosting circuit of a semiconductor memory device, wherein a sensing control signal having a first pulse width and a second delay are activated after a first delay period is input by inputting a chip master clock for determining a standby cycle and an active cycle. A first circuit means which is activated after a lapse of time and generates a latch control signal having a second pulse width, and generates a detection signal informing the potential state of the current boosted voltage in response to the sensing control signal and the latch control signal; Second circuit means, a third circuit means for generating a boosted voltage generation control signal that is activated simultaneously with the sense signal in response to the chip master clock, and the standby cycle according to the sensed signal and the boosted voltage generation control signal And first and second step-up voltage generating circuits respectively operating in the active cycle.

Description

반도체메모리소자의 활성싸이클에서 사용되는 승압회로Step-up circuits used in active cycles of semiconductor memory devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제6도는 본 발명의 일실시예에 따른 승압회로의 구성을 보여주는 블럭도, 제7도는 제6도에서 사용된 감지제어회로의 회로도, 제8도는 제6도에서 사용된 승압전압감지회로의 회로도.6 is a block diagram showing a configuration of a boost circuit according to an embodiment of the present invention, FIG. 7 is a circuit diagram of a sensing control circuit used in FIG. 6, and FIG. 8 is a circuit diagram of a boost voltage sensing circuit used in FIG. .

Claims (2)

반도체 메모리소자의 승압회로에 있어서, 대기싸이클과 활성싸이클을 결정하는 칩마스터클럭을 입력하여 제1지연기간이 경과한 후에 활성화되며 제1펄스폭을 가진 감지제어신호와 제2지연시간이 경과한 후에 활성화되며 제2펄스폭을 가지는 래치제어신호를 발생하는 제1회로수단과, 상기 감지제어신호와 상기 래치제어신호에 응답하여 현재의 승압전압의 전위상태를 알리는 감지신호를 발생하는 제2회로수단과, 상기 칩마스터 클럭에 응답하여 상기 감지신호와 동시에 활성화되는 승압전압발생 제어신호를 발생하는 제3회로수단과, 상기 감지신호와 상기 승압전압발생 제어신호에 따라 상기 활성싸이클에서 동작하는 승압전압발생회로를 구비함을 특징으로 하는 승압회로.In a boost circuit of a semiconductor memory device, a chip master clock for determining a standby cycle and an active cycle is input and activated after a first delay period, and a sensing control signal having a first pulse width and a second delay time have passed. A first circuit means which is activated later and generates a latch control signal having a second pulse width, and a second circuit which generates a sense signal informing a potential state of a current boosted voltage in response to the sense control signal and the latch control signal. Means, third circuit means for generating a boosted voltage generation control signal that is activated simultaneously with the sense signal in response to the chip master clock, and boosted voltage that operates in the active cycle in accordance with the sensed signal and the boosted voltage generation control signal A boosting circuit comprising a voltage generating circuit. 반도체 메모리소자의 승압회로에 있어서, 대기싸이클과 활성싸이클을 결정하는 칩마스터클럭을 입력하여 제1지연기간이 경과한 후에 활성화되며 제1펄스폭을 가진 감지제어신호와 제2지연시간이 경과한 후에 활성화되며 제2펄스폭을 가지는 래치제어신호를 발생하는 제1회로수단과, 상기 감지제어신호와 상기 래치제어신호에 응답하여 현재의 승압전압의 전위상태를 알리는 제1감지신호를 발생하는 제2회로수단과, 상기 제1감지신호를입력하고 상기 칩마스터클럭의 제어에 따라 제2감지신호를 발생하는 제3회로수단과, 상기 칩마스터클럭에 응답하여 상기 제2감지신호와동시에 활성화되는 승압전압 발생제어신호를 발생하는 제4회로수단과, 상기 제2감지신호와 상기 승압전압발생제어신호에 따라 상기 대기싸이클 및 활성싸이클에서 각각 동작하는 제1 및 제2승압전압발생회로를 구비함을 특징으로 하는 승압회로.In a boost circuit of a semiconductor memory device, a chip master clock for determining a standby cycle and an active cycle is input and activated after a first delay period, and a sensing control signal having a first pulse width and a second delay time have passed. First circuit means which is activated later and generates a latch control signal having a second pulse width, and a first sense signal that generates a first sense signal informing a potential state of a current boosted voltage in response to the sensing control signal and the latch control signal. Two circuit means, a third circuit means for inputting the first sense signal and generating a second sense signal under control of the chip master clock, and activated simultaneously with the second sense signal in response to the chip master clock Fourth circuit means for generating a boosted voltage generation control signal, and operating in the standby cycle and the active cycle in accordance with the second sense signal and the boosted voltage generation control signal, respectively. And a first boosting voltage generating circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038503A 1994-12-29 1994-12-29 Boost circuit of semiconductor memory device KR0137317B1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1019940038503A KR0137317B1 (en) 1994-12-29 1994-12-29 Boost circuit of semiconductor memory device
TW084113127A TW282544B (en) 1994-12-29 1995-12-09
DE19547796A DE19547796C2 (en) 1994-12-29 1995-12-20 Boost voltage circuit for a semiconductor memory device
JP7342653A JP2828942B2 (en) 1994-12-29 1995-12-28 Semiconductor memory booster circuit
FR9515663A FR2729020B1 (en) 1994-12-29 1995-12-28 BOOST CIRCUIT USED IN AN ACTIVE STATE OF A SEMICONDUCTOR MEMORY DEVICE
CN95120640A CN1045838C (en) 1994-12-29 1995-12-29 Boosting coltage circuit used in active cycle of a semiconductor memory device
GB9526716A GB2296593B (en) 1994-12-29 1995-12-29 Boosting voltage circuit for semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038503A KR0137317B1 (en) 1994-12-29 1994-12-29 Boost circuit of semiconductor memory device

Publications (2)

Publication Number Publication Date
KR960025707A true KR960025707A (en) 1996-07-20
KR0137317B1 KR0137317B1 (en) 1998-04-29

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KR1019940038503A KR0137317B1 (en) 1994-12-29 1994-12-29 Boost circuit of semiconductor memory device

Country Status (7)

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JP (1) JP2828942B2 (en)
KR (1) KR0137317B1 (en)
CN (1) CN1045838C (en)
DE (1) DE19547796C2 (en)
FR (1) FR2729020B1 (en)
GB (1) GB2296593B (en)
TW (1) TW282544B (en)

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KR100741471B1 (en) * 2006-09-29 2007-07-20 삼성전자주식회사 Latch-free boosting scheme

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KR0142963B1 (en) * 1995-05-17 1998-08-17 김광호 Semiconductor memory apparatus having the boosting circuit
KR0172337B1 (en) * 1995-11-13 1999-03-30 김광호 Semiconductor memory device
US6094395A (en) * 1998-03-27 2000-07-25 Infineon Technologies North America Corp. Arrangement for controlling voltage generators in multi-voltage generator chips such as DRAMs
CN1299432C (en) * 2001-10-29 2007-02-07 旺宏电子股份有限公司 Drive voltage generator for reducing the effect of work voltage and temperature
KR100846484B1 (en) 2002-03-14 2008-07-17 삼성전자주식회사 Rotation magnetron in magnetron electrode and method of manufacturing the same and sputtering apparatus with the same
JP5137545B2 (en) * 2006-12-25 2013-02-06 株式会社半導体エネルギー研究所 Semiconductor device and driving method thereof
US9502119B2 (en) * 2014-11-20 2016-11-22 Samsung Electronics Co., Ltd. Distributed capacitive delay tracking boost-assist circuit

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KR100741471B1 (en) * 2006-09-29 2007-07-20 삼성전자주식회사 Latch-free boosting scheme

Also Published As

Publication number Publication date
JPH08235859A (en) 1996-09-13
CN1045838C (en) 1999-10-20
FR2729020B1 (en) 1998-07-10
FR2729020A1 (en) 1996-07-05
TW282544B (en) 1996-08-01
GB9526716D0 (en) 1996-02-28
JP2828942B2 (en) 1998-11-25
DE19547796A1 (en) 1996-07-11
DE19547796C2 (en) 1998-04-16
GB2296593B (en) 1997-07-23
GB2296593A (en) 1996-07-03
KR0137317B1 (en) 1998-04-29
CN1127919A (en) 1996-07-31

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