KR960025104A - Computer system with multiple processors in master or slave relationship - Google Patents

Computer system with multiple processors in master or slave relationship Download PDF

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Publication number
KR960025104A
KR960025104A KR1019940038270A KR19940038270A KR960025104A KR 960025104 A KR960025104 A KR 960025104A KR 1019940038270 A KR1019940038270 A KR 1019940038270A KR 19940038270 A KR19940038270 A KR 19940038270A KR 960025104 A KR960025104 A KR 960025104A
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KR
South Korea
Prior art keywords
computer system
master
slave relationship
processor
program
Prior art date
Application number
KR1019940038270A
Other languages
Korean (ko)
Other versions
KR0147611B1 (en
Inventor
하문수
오학서
박준호
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019940038270A priority Critical patent/KR0147611B1/en
Publication of KR960025104A publication Critical patent/KR960025104A/en
Application granted granted Critical
Publication of KR0147611B1 publication Critical patent/KR0147611B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multi Processors (AREA)
  • Stored Programmes (AREA)

Abstract

본 발명은 주종 관계의 복수의 프로세서를 가진 컴퓨터 시스템에 관한 것이다.The present invention relates to a computer system having a plurality of processors in master or slave relationship.

본 발명은 주종 관계의 복수의 프로세서를 가지는 컴퓨터 시스템에 있어서, 상기 복수의 프로세서부중 적어도 한 개의 서브 프로세서부는 프로그램 메모리 및 데이타 메모리가 모두 램으로 구성되어 있는 점에 그 특징이 있다.The present invention is characterized in that a computer system having a plurality of processors having a master or slave relationship, wherein at least one of the plurality of processor units has a program memory and a data memory all composed of RAM.

이와 같은 구성의 본 발명은 서브 프로세서의 프로그램 메모리가 종래와는 달리 RAM으로 되어 있으므로, 서브 프로세서의 프로그램 개발을 용이하게 할 수 있을 뿐만 아니라, 사용자는 프로그램 개발 완료 후에도 직접 프로그램을 변경할 수 있는 장점이 있다.According to the present invention having the above configuration, since the program memory of the subprocessor is RAM, unlike the related art, not only can the program development of the subprocessor be facilitated, but the user can directly change the program even after the program development is completed. have.

Description

주종 관계의 복수의 프로세서를 가진 컴퓨터 시스템Computer system with multiple processors in master or slave relationship

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 주종 관계의 프로세서를 가진 컴퓨터 시스템의 개략적인 시스템 구성도, 제3도는 본 발명에 따른 컴퓨터 시스템에 있어서, 메인 프로세서와 서브 프로세서의 프로그램 램과의 인터페이스 회로의 개략적인 구성도, 제4도는 본 발명에 따른 컴퓨터 시스템에 있어서, 메인 프로세서로부터 서브 프로세서의 다운 로드 알고리즘을 나타내 보이는 흐름도.2 is a schematic system configuration diagram of a computer system having a master / slave processor according to the present invention, and FIG. 3 is a schematic configuration of an interface circuit between a main processor and a program RAM of a sub-processor in the computer system according to the present invention. 4 is a flowchart showing a download algorithm of a subprocessor from a main processor in a computer system according to the present invention.

Claims (3)

메인 프로세서부와 서브 프로세서부의 주종 관계를 가지는 복수의 프로세서부를 가지는 컴퓨터 시스템에있어서, 상기 복수의 프레세서부중 적어도 한 개의 서브 프로세서부는 프로그램 메모리 및 데이타 메모리가 모두 램으로 구성되어 있는 것을 특징으로 하는 주종 관계의 복수의 프로세서를 가진 컴퓨터 시스템.A computer system having a plurality of processor units having a main relationship between a main processor unit and a subprocessor unit, wherein at least one of the plurality of processor units includes both a program memory and a data memory as RAM. Computer system with multiple processors in master or slave relationship. 제1항에 있어서, 상기 복수의 프로세서부의 프로그램 영역이 복수의 영역으로 분할되어 있는 것을 특징으로 하는 주종 관계의 복수의 프로세서를 가진 컴퓨터 시스템The computer system according to claim 1, wherein program areas of said plurality of processor sections are divided into a plurality of areas. 제1항에 있어서, 상기 메인 프로세서부와 서브 프로세서부 사이에 상호 신호를 주고 받을 수 있도록 하는 별도의 인터페이스회로부가 설치되어 있는 것을 특징으로 하는 주종 관계의 복수의 프로세서를 가진 컴퓨터 시스템.The computer system according to claim 1, wherein a separate interface circuit part is provided between the main processor part and the sub processor part to exchange signals with each other. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038270A 1994-12-28 1994-12-28 Processor KR0147611B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940038270A KR0147611B1 (en) 1994-12-28 1994-12-28 Processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038270A KR0147611B1 (en) 1994-12-28 1994-12-28 Processor

Publications (2)

Publication Number Publication Date
KR960025104A true KR960025104A (en) 1996-07-20
KR0147611B1 KR0147611B1 (en) 1998-09-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940038270A KR0147611B1 (en) 1994-12-28 1994-12-28 Processor

Country Status (1)

Country Link
KR (1) KR0147611B1 (en)

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Publication number Publication date
KR0147611B1 (en) 1998-09-15

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