KR960015718A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR960015718A
KR960015718A KR1019940027291A KR19940027291A KR960015718A KR 960015718 A KR960015718 A KR 960015718A KR 1019940027291 A KR1019940027291 A KR 1019940027291A KR 19940027291 A KR19940027291 A KR 19940027291A KR 960015718 A KR960015718 A KR 960015718A
Authority
KR
South Korea
Prior art keywords
forming
barrier layer
metal
psg film
solder
Prior art date
Application number
KR1019940027291A
Other languages
Korean (ko)
Other versions
KR0141420B1 (en
Inventor
백종무
백준영
임승무
홍기석
이근혁
Original Assignee
곽정소
한국전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 곽정소, 한국전자 주식회사 filed Critical 곽정소
Priority to KR1019940027291A priority Critical patent/KR0141420B1/en
Publication of KR960015718A publication Critical patent/KR960015718A/en
Application granted granted Critical
Publication of KR0141420B1 publication Critical patent/KR0141420B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191—Forming a passivation layer after forming the bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 제조방법에 관한 것으로, 기판 위에 금속물질을 증착시킨 후 패터닝하여 금속패드를 형성하는 공정과, 상기 금속패드 양측에 표면을 안정화시키기 위한 패시베이션층을 형성하는 공정과, 상기 금속패드 및 패시베이션층 위에 금속장벽층을 형성하는 공정과, 상기 금속장벽층 위에 솔더범프 형성영역 의의 다른 부분을 보호하기 위해 PSG막을 형성한 후 하부의 금속장벽층이 노출되도록 선택적으로 식각하는 공정과, 상기 금속장벽층을 접촉하도록 솔더를 전기금속도금한 후 리플로우하여 솔더범프를 형성하는 공정과, 상기 PSG막을 제거하는 공정을 포함하여 구성되며, 상기와 같이 솔더의 전기금속도금시 솔더에 비해 제거가 쉬운 PSG막으로 다른 부분을 보호하고, 리플로우 후 상기 PSG막을 제거함으로써 도금된 솔더의 식각을 최소화할 수 있으며, 상기 솔더의 PSG막에 대한 웨팅성이 떨어지는 특성과 표면장력을 이용하여 솔더를 용이하게 양질을 반구형으로 형성할 수 있는 효과가 있다,The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a metal pad by depositing a metal material on a substrate and then patterning the metal pad; forming a passivation layer for stabilizing surfaces on both sides of the metal pad; Forming a metal barrier layer on the pad and passivation layer, forming a PSG film on the metal barrier layer to selectively protect the other portions of the solder bump forming region, and then selectively etching the metal barrier layer to expose the lower metal barrier layer; Electroplating the solder to contact the metal barrier layer and then reflowing to form solder bumps, and removing the PSG film, as described above. Easy-to-use PSG film protects other parts and removes the PSG film after reflow to eliminate etching of plated solder Can digest and, by using the properties and the surface tension gateway tingseong falls on PSG film of the solder has an effect capable of easily forming a good quality with a semi-spherical solder,

Description

반도체소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 반도체소자의 제조방법을 도시한 단면도.2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the present invention.

Claims (4)

기판 위에 금속물질을 증착시킨 후 패터닝하여 금속패드를 형성하는 공정과, 상기 금속패드 양측에 표면을 안정화시키기 위한 패시베이션층을 형성하는 공정과, 상기 금속패드 및 패시베이션층 위에 금속장벽층을 형성하는 공정과, 상기 금속장벽층 위에 솔더범프 형성영역 외의 다른 부분을 보호하기 위해 PSG막을 형성한 후 하부의 금속장벽층이 노출되도록 선택적으로 식각하는 공정과, 상기 금속장벽층과 접촉하도록 솔더를 전기 금속도금한 후 리플로우하여 솔더범프를 형성하는 공정과, 상기 PSG막을 제거하는 공정을 포함하여 구성된 것을 특징으로 하는 반도체소자의 제조방법.Forming a metal pad by depositing and patterning a metal material on a substrate, forming a passivation layer for stabilizing surfaces on both sides of the metal pad, and forming a metal barrier layer on the metal pad and the passivation layer And forming a PSG film on the metal barrier layer to protect other portions other than the solder bump forming region, and selectively etching the lower metal barrier layer to expose the lower metal barrier layer, and electroplating solder to contact the metal barrier layer. And then reflowing to form solder bumps, and removing the PSG film. 제1항에 있어서, 상기 금속패드는 그 두께가 20㎛ 이상임을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the metal pad has a thickness of 20 μm or more. 제1항에 있어서, 상기 PSG막은 PECVD법에 의해 형성됨을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the PSG film is formed by PECVD. 제1항 또는 제3항에 있어서, 상기 PSG막은 그 두께가 0.5㎛ 정도임을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the PSG film has a thickness of about 0.5 μm. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940027291A 1994-10-25 1994-10-25 Fabrication method of semiconductor device KR0141420B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940027291A KR0141420B1 (en) 1994-10-25 1994-10-25 Fabrication method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940027291A KR0141420B1 (en) 1994-10-25 1994-10-25 Fabrication method of semiconductor device

Publications (2)

Publication Number Publication Date
KR960015718A true KR960015718A (en) 1996-05-22
KR0141420B1 KR0141420B1 (en) 1998-07-15

Family

ID=19395831

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940027291A KR0141420B1 (en) 1994-10-25 1994-10-25 Fabrication method of semiconductor device

Country Status (1)

Country Link
KR (1) KR0141420B1 (en)

Also Published As

Publication number Publication date
KR0141420B1 (en) 1998-07-15

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