KR960015259A - Multiple Ethernet Bus Arbitration Processing System Using Backplane Board - Google Patents

Multiple Ethernet Bus Arbitration Processing System Using Backplane Board Download PDF

Info

Publication number
KR960015259A
KR960015259A KR1019940026518A KR19940026518A KR960015259A KR 960015259 A KR960015259 A KR 960015259A KR 1019940026518 A KR1019940026518 A KR 1019940026518A KR 19940026518 A KR19940026518 A KR 19940026518A KR 960015259 A KR960015259 A KR 960015259A
Authority
KR
South Korea
Prior art keywords
ethernet
repeater
board
backplane
arbitration processing
Prior art date
Application number
KR1019940026518A
Other languages
Korean (ko)
Other versions
KR0158940B1 (en
Inventor
유동관
Original Assignee
정장호
엘지정보통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정장호, 엘지정보통신 주식회사 filed Critical 정장호
Priority to KR1019940026518A priority Critical patent/KR0158940B1/en
Publication of KR960015259A publication Critical patent/KR960015259A/en
Application granted granted Critical
Publication of KR0158940B1 publication Critical patent/KR0158940B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40084—Bus arbitration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40013—Details regarding a bus controller
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/417—Bus networks with decentralised control with deterministic access, e.g. token passing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)

Abstract

본 발명은 다중 이더넷 중계기 시스템과 관련된 것으로서, 종래에는 이러한 시스템에서 각각의 이더넷중계기보드에서 제각기의 이더넷중재기나 레벨비교회로 등을 구비하고 있기 때문에 그 시스템의 구성을 복잡하게 할 뿐만 아니라 시스템의 처리효율을 저하시킨다는 문제점이 있었다.The present invention relates to a multiple Ethernet repeater system, and in the related art, since each of the Ethernet repeater boards includes their respective Ethernet intermediators and level comparators, the system not only complicates the configuration of the system but also the processing efficiency of the system. There was a problem of lowering.

본 발명은 종래의 이러한 문제점을 개선할 수 있도록 통상의 이더넷중재기와 레벨 비교회로가 각기 중계기보드측에 구비되어져 있지 않고 이더넷중계기콘트롤러(31)만 구비되어져 있는 다수의 중계기보드(3)와, 이 중계기보드(3)측의 이더넷중계기콘트롤러(31)와 연결되어져서 버스사용 중재 처리를 공통으로 처리하여 줄 수 있는 백플레인중재로직(41)를 갖는 백플레인보드(40)와의 관련 구성으로 이루어져 있는 다중 이더넷 중재 처리시스템을 제공하는데 있다.The present invention provides a plurality of repeater boards (3), each of which is equipped with only an Ethernet repeater controller (31) without a conventional Ethernet intermediator and a level comparison circuit on the side of the repeater board, so as to improve such a conventional problem. This is connected to the Ethernet repeater controller 31 on the side of the repeater board 3, and is composed of a related configuration with the backplane board 40 having a backplane mediation logic 41 which can handle bus arbitration processing in common. To provide an Ethernet arbitration processing system.

Description

백플레인 보드를 이용한 다중 이더넷 버스 중재 처리 시스템Multiple Ethernet Bus Arbitration Processing System Using Backplane Board

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 이더넷 버스 중재 로직의 시스템 회로 블럭도.2 is a system circuit block diagram of Ethernet bus arbitration logic in accordance with the present invention.

Claims (1)

이더넷버스(EB)가 구비되어져 있는 백플레인보드와, 이더넷버스(EB)에 연결되어져 있는 다수의 중계기보드로 이루어져 있는 다중 이더넷 시스템에 있어서, 통상의 이더넷중재기와 레벨비교회로가 각기 중계기보드측에 구비되어져 있지 않고 이더넷중계기콘트롤러(31)만 구비되어져 있는 다수의 중계기보드(3)와, 이 중계기보드(3)측의 이더넷중계기콘트롤러(31)와 연결되어져서 버스사용 중재 처리를 공통으로 처리하여 줄 수 있는 백플레인중재로직(41)을 갖는 백플레인보드(40)와의 관련구성으로 이루어져 있는 것을 특징으로 하는 다중 이더넷 중재 처리 시스템.In a multi-Ethernet system consisting of a backplane board equipped with an Ethernet bus (EB) and a plurality of repeater boards connected to the Ethernet bus (EB), a normal Ethernet intermediary and a level comparison path are placed on the repeater board side. It is connected to a plurality of repeater boards 3, which are not provided but only the Ethernet repeater controller 31, and the Ethernet repeater controller 31 on the side of the repeater board 3 to process the bus arbitration process in common. Multiple Ethernet arbitration processing system, characterized in that it consists of a related configuration with a backplane board (40) having a backplane intermediate logic (41). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940026518A 1994-10-17 1994-10-17 Multiple ethernet bus arbitration processing system using back-plane board KR0158940B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940026518A KR0158940B1 (en) 1994-10-17 1994-10-17 Multiple ethernet bus arbitration processing system using back-plane board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940026518A KR0158940B1 (en) 1994-10-17 1994-10-17 Multiple ethernet bus arbitration processing system using back-plane board

Publications (2)

Publication Number Publication Date
KR960015259A true KR960015259A (en) 1996-05-22
KR0158940B1 KR0158940B1 (en) 1999-02-18

Family

ID=19395237

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940026518A KR0158940B1 (en) 1994-10-17 1994-10-17 Multiple ethernet bus arbitration processing system using back-plane board

Country Status (1)

Country Link
KR (1) KR0158940B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100334417B1 (en) * 1999-11-22 2002-05-03 석한진 Backplane system with a point-to-point bus architecture

Also Published As

Publication number Publication date
KR0158940B1 (en) 1999-02-18

Similar Documents

Publication Publication Date Title
ATE163226T1 (en) HEAT EXCHANGER
KR840006880A (en) Power system
CA2138263A1 (en) Multiprocessor
DE3787492D1 (en) Distributed voice data exchange in multi-stage connection networks.
CA2323452A1 (en) Disturbance free update of data
CA2332298A1 (en) Multiconfiguration backplane
DE69200544D1 (en) Integral edge connector for printed circuit boards.
KR960015259A (en) Multiple Ethernet Bus Arbitration Processing System Using Backplane Board
ES2085502T3 (en) COUPLING PROVISION OF INVESTMENT-ATM AT LEAST DUPLICATED, OF TWO PHASES WITH (2NX2N) -MULTIPLE COUPLING.
KR970068365A (en) Communication control device and communication system using the same
BR9910544A (en) Low power counter
DE69109368D1 (en) Fuse unit, in particular for printed circuits.
NO20000861L (en) Modular protective relay with sub-modules
ATE218464T1 (en) SYSTEM FOR STORING ITEMS, ESPECIALLY BOATS
DE59603583D1 (en) BUFFER CIRCUIT ARRANGED ON AN ASSEMBLY
KR900018810A (en) Processor unit network
DE59003669D1 (en) Special polydiorganosiloxane block copolycarbonates.
EP0373299A3 (en) Method and apparatus for memory routing scheme
KR960015260A (en) Multiple Ethernet Bus Selection Logic Using Backplane Transport
WO1995027952A3 (en) Data processing apparatus
SE9404556D0 (en) Magazine-related bus arrangement
TW359785B (en) Computer-aided method to partition of an electronic circuit
KR960015258A (en) Isolation Logic with Backplane Arbitrator
KR960015261A (en) Bus Selection Logic in Multiple Ethernet Systems
KR970049736A (en) Cluster Connection Architecture Using Crossbar Switch in Parallel Processing Computer System

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010425

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee