KR960014956A - Test data input device with boundary scan structure - Google Patents
Test data input device with boundary scan structure Download PDFInfo
- Publication number
- KR960014956A KR960014956A KR1019940027805A KR19940027805A KR960014956A KR 960014956 A KR960014956 A KR 960014956A KR 1019940027805 A KR1019940027805 A KR 1019940027805A KR 19940027805 A KR19940027805 A KR 19940027805A KR 960014956 A KR960014956 A KR 960014956A
- Authority
- KR
- South Korea
- Prior art keywords
- test data
- tck
- signal
- output
- inverted
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318566—Comparators; Diagnosing the device under test
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
본 발명은 IEEE(lnstitute of Electrical and Electronics Engineers)에서 규정한 바운더리 스캔 구조(Boundary-Scan Architecture)에 관한 것으로서, 병직렬 시프트 레지스터(30)에 테스트 데이타를 병렬로 저장시긴 후에 비교회로(40)를 이용하여 TCK 형성회로(20)로 하여금 시스템 클럭(SCR)에 동기되며 테스트 데이타의 갯수에 해당하는 반전 TCK 및 TCK를 형성케 하는 것이다. 그리고, 병직렬 시프트 레지스터(40)는 반전 TCK에 동기되어 저장된 테스트 데이타를 집적회로(50)에 인가하게 하므로써, 집적회로(50)는 TCK의 상승에지에 동기되어 테스트 데이타를 직렬로 입력할 수 있는 것이다.The present invention relates to a boundary-scan architecture defined by the Institute of Electrical and Electronics Engineers (IEEE), wherein the comparison circuit 40 is stored in parallel after storing test data in a parallel shift register 30. This allows the TCK forming circuit 20 to form inverted TCKs and TCKs that are synchronized to the system clock SCR and correspond to the number of test data. Then, the parallel shift register 40 applies the test data stored in synchronization with the inverted TCK to the integrated circuit 50 so that the integrated circuit 50 can input the test data in series in synchronization with the rising edge of the TCK. It is.
따라서, 본 발명은 프로세서가 집적회로에 테스트 데이타를 입력하는데 소요되는 시간을 단축할 수 있게되어 프로세서의 효율성을 높일 수 있다는 효과가 있다.Therefore, the present invention can shorten the time required for the processor to input test data to the integrated circuit, thereby increasing the efficiency of the processor.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도는 본 발명에 따른 바운더리 스캔 구조의 테스트 데이타입력장치의 블럭도,2 is a block diagram of a test data input apparatus having a boundary scan structure according to the present invention;
제3도는 본 발명에 따른 바운더리 스캔 구조의 테스트 데이타입력장치의 주요 부분 파형도.3 is a main partial waveform diagram of a test data input device having a boundary scan structure according to the present invention.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940027805A KR970000820B1 (en) | 1994-10-28 | 1994-10-28 | Test data input circuit of boundary-scan architecture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940027805A KR970000820B1 (en) | 1994-10-28 | 1994-10-28 | Test data input circuit of boundary-scan architecture |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960014956A true KR960014956A (en) | 1996-05-22 |
KR970000820B1 KR970000820B1 (en) | 1997-01-20 |
Family
ID=19396232
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940027805A KR970000820B1 (en) | 1994-10-28 | 1994-10-28 | Test data input circuit of boundary-scan architecture |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970000820B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3401523B2 (en) * | 1999-01-11 | 2003-04-28 | デュアキシズ株式会社 | Communication element and communication device using the same |
-
1994
- 1994-10-28 KR KR1019940027805A patent/KR970000820B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR970000820B1 (en) | 1997-01-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100523716B1 (en) | Register without restriction of number of mounted memory devices and memory module having the same | |
KR910006735A (en) | Ease of Testing Circuits in Digital Integrated Circuits | |
KR880009381A (en) | Semiconductor integrated circuit device | |
TWI221926B (en) | A multi-time domain logic system and related method | |
JPH06105285B2 (en) | Semiconductor integrated circuit device | |
US9264023B2 (en) | Scannable flop with a single storage element | |
JP2937326B2 (en) | Test circuit for logic circuits | |
KR960014956A (en) | Test data input device with boundary scan structure | |
TW490568B (en) | Timing generation circuit for semiconductor test system | |
JPH10133768A (en) | Clock system and semiconductor device, and method for testing semiconductor device, and cad device | |
JP4649064B2 (en) | Output circuit | |
US6748563B1 (en) | Method and apparatus for testing path delays in a high-speed boundary scan implementation | |
JP3368572B2 (en) | Period generator | |
KR960014957A (en) | Test data output device with boundary scan structure | |
KR970000260B1 (en) | Parallel inputable boudary-scan architecture | |
JP2897540B2 (en) | Semiconductor integrated circuit | |
KR100991997B1 (en) | An internal clock generator | |
KR930006540A (en) | Partial multiplier selection circuit of multiplication circuit | |
KR0145797B1 (en) | Parallel outputtable boundary-scan architecture | |
JPH04215079A (en) | Timing generator | |
KR0145789B1 (en) | Test clock generator of boundary-scan architecture | |
JP3425580B2 (en) | Test signal generation circuit for semiconductor integrated circuit | |
JPH09145798A (en) | Timing signal generator | |
JP2504949B2 (en) | Shift register | |
JPH04361179A (en) | Semiconductor integrated circuit device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
LAPS | Lapse due to unpaid annual fee |