KR960008744B1 - Variable length decoding apparatus and method - Google Patents
Variable length decoding apparatus and method Download PDFInfo
- Publication number
- KR960008744B1 KR960008744B1 KR92026038A KR920026038A KR960008744B1 KR 960008744 B1 KR960008744 B1 KR 960008744B1 KR 92026038 A KR92026038 A KR 92026038A KR 920026038 A KR920026038 A KR 920026038A KR 960008744 B1 KR960008744 B1 KR 960008744B1
- Authority
- KR
- South Korea
- Prior art keywords
- code word
- bit
- variable length
- address
- memory
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The variable length decoder which separates the code word from the inputted bit stream by rearranging a code word table recommended by CCITT and can decode the code word by variable length decoding(VLD) and comprises: a memory(22) which stores a table for VLD corresponding to the code word to use the code word as address; a low address generating part which generates the low address of a memory(22), and comprises a "1" detecting and maintaining part(16), an AND gate(18) and a shifter(20); a high address generating part(24) which generates the high address of the memory(22) by bit "0" prior to the first bit "1" of the code word; a clock masking signal generating part(26) which controls the high address generation before the first bit "1" of each code word is detected and controls the low address generation after the first bit "1" of each code word is detected, and comprises a counter(10), a latch(12) and a clock masking(14).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR92026038A KR960008744B1 (en) | 1992-12-29 | 1992-12-29 | Variable length decoding apparatus and method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR92026038A KR960008744B1 (en) | 1992-12-29 | 1992-12-29 | Variable length decoding apparatus and method |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940017254A KR940017254A (en) | 1994-07-26 |
KR960008744B1 true KR960008744B1 (en) | 1996-06-29 |
Family
ID=19347150
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR92026038A KR960008744B1 (en) | 1992-12-29 | 1992-12-29 | Variable length decoding apparatus and method |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960008744B1 (en) |
-
1992
- 1992-12-29 KR KR92026038A patent/KR960008744B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR940017254A (en) | 1994-07-26 |
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