KR960003110A - Timing restoration system - Google Patents

Timing restoration system Download PDF

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Publication number
KR960003110A
KR960003110A KR1019940013288A KR19940013288A KR960003110A KR 960003110 A KR960003110 A KR 960003110A KR 1019940013288 A KR1019940013288 A KR 1019940013288A KR 19940013288 A KR19940013288 A KR 19940013288A KR 960003110 A KR960003110 A KR 960003110A
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KR
South Korea
Prior art keywords
output signal
signal
timing
phase error
output
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KR1019940013288A
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Korean (ko)
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KR960010856B1 (en
Inventor
권오상
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배순훈
대우전자 주식회사
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Priority to KR1019940013288A priority Critical patent/KR960010856B1/en
Publication of KR960003110A publication Critical patent/KR960003110A/en
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Publication of KR960010856B1 publication Critical patent/KR960010856B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

본 발명은 송신단으로부터 수신된 신호의 타이밍을 복원하기 위한 시스템으로써, 상기 수신된 아나로그 신호를 디지탈 신호로 변환하기 위한 아날로그/디지털(A/D) 변환기(10)와; 상기 A/D변환기외 출력 신호로부터 타이밍 위상오차를 추정하기 위한 타이밍 위상오차 추정 수단(2l0)과; 상기 타이밍 위상오차 추정 수단의 출력 신호의 평균값을 구하기 위한 수단(220)과; 상기 타이밍 위상오차 추정 수단의 출력신호로부터 행업 발생여부를 판단하기 위한 제1판단 수단(250)과; 상기 수단(220)의 출력 신호로부터 행업 발생여부를 판단하기 위한 제2판단 수단(250)과; 상기 수단(220)에서 출력되는 타이밍 위상오차값과 행업발생시 대체하기 위한 기설정된 타이밍 오차값을 외부로 부터 수신되는 소정의 제어신호의 의해 질환 하기 위한 질환 수단(230)과; 상기 제l판단 수단의 출력신호와 상기 제2판단 수단의 출력신호에 응답하여 상기 질환 수단을 제어하기 위해 제어신호를 생성하기 위한 제1제어수단(260) 및 상기 질환 수단의 출력신호를 입력하여 상기 A/D변환기의 복합 시설을 제어하기 위한 제2제어 수단(80)을 구비한다. 따라서 행업 현상을 방지할 수 있다.The present invention provides a system for recovering the timing of a signal received from a transmitter, comprising: an analog / digital (A / D) converter (10) for converting the received analog signal into a digital signal; Timing phase error estimating means (210) for estimating timing phase error from the A / D converter output signal; Means (220) for obtaining an average value of the output signal of the timing phase error estimation means; First judging means (250) for judging whether a hangup has occurred from the output signal of the timing phase error estimating means; Second judging means (250) for judging whether a hang-up has occurred from the output signal of the means (220); Disease means (230) for causing a disease caused by a predetermined control signal received from the outside to replace a timing phase error value output from the means (220) and a preset timing error value for a hangup occurrence; A first control means 260 for generating a control signal for controlling the disease means in response to an output signal of the first determination means and an output signal of the second determination means and an output signal of the disease means Second control means (80) for controlling the complex facility of the A / D converter is provided. Therefore, the hangup phenomenon can be prevented.

Description

타이밍 복원 시스템Timing restoration system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 제1도 PLL 회로의 동작을 설명하기 위한 그래프.2 is a graph for explaining the operation of the PLL circuit of FIG.

제3도는 본 발명에 의한 타이밍 복원 시스템의 일실시예에 따른 블럭도.3 is a block diagram according to an embodiment of a timing recovery system according to the present invention.

Claims (3)

송신단으로부터 수신된 신호의 타이밍을 복원하기 위한 시스템에 있어서, 상기 수신된 아날로그 신호를 디지탈 신호로 변환하기 위한 아날로그/디지탈(A/D) 변환기(10)와 ; 상기 A/D 변환기의 출력 신호로부터 타이밍 위상 오차를 추정하기 위한 타이밍 위상 오차 추정 수단(210)과 ; 상기 타이밍 위상 오차 추정 수단의 출력 신호의 평균값을 구하기 위한 수단(220)과 , 상기 타이밍 위상 오차 추정 수단의 출력 신호로부터 행업 발생 여부를 판단하기 위한 제 1판단 수단(240)과 : 상기 수단(220)의 출력 신호로부터 행업 발생 여부를 판단하기 위한 제 2판단 수단(250)과 : 상기 수단(220)에서 출력되는 타이밍 위상 오차값과 행업 발생시 대체하기 위한 기설정된 타이밍 오차값을 외부로부터 수신되는 소정의 제어 신호에 의해 절환하기 위한 절환 수단(230)과 ; 상기 제 1판단 수단 출력 신호와 상기 제 2.판단 수단의 출력 신호에 응답하여 상기 절환 수단을 제어하기 위해 제어 신호를 생성하기 위한 제 1제어 수단(260) ; 및 상기 절환 수단의 출력 신호를 입력하여 상기 A/D 변환기의 표본화 시점을 제어하기 위한 제 2제어 수단(80)을 포함하는 타이밍 복원 시스템.CLAIMS 1. A system for recovering timing of a signal received from a transmitter, comprising: an analog / digital (A / D) converter (10) for converting the received analog signal into a digital signal; Timing phase error estimation means (210) for estimating timing phase error from an output signal of the A / D converter; Means 220 for obtaining an average value of the output signal of the timing phase error estimating means, first determination means 240 for judging whether a hangup has occurred from the output signal of the timing phase error estimating means, and the means 220 Second determination means 250 for determining whether a hangup has occurred from an output signal of the control unit; and a predetermined timing error value output from the means 220 and a predetermined timing error value for replacing the hangup from the outside. Switching means (230) for switching by a control signal of; First control means (260) for generating a control signal for controlling the switching means in response to the first judging means output signal and the output signal of the second judging means; And second control means (80) for inputting an output signal of the switching means to control a sampling time point of the A / D converter. 제1항에 있어서, 상기 제 1판단 수단(240)은 상기 타이밍 위상 오차 추정 수단의 출력 신호에 대하여 절대값을 계산하는 절대값 계산 회로(241)와; 상기 절대값 계산 회로의 출력에 대하여 평균값을 구하는 평균기(242); 및 상기 평균기의 출력을 소정의 임계치와 비교하는 비교기(243)를 포함하는 타이밍 복원 시스템.2. The apparatus of claim 1, wherein the first judging means (240) comprises: an absolute value calculating circuit (241) for calculating an absolute value with respect to an output signal of the timing phase error estimating means; An averager (242) for obtaining an average value with respect to the output of the absolute value calculating circuit; And a comparator (243) for comparing the output of the averager with a predetermined threshold. 제1항에 있어서, 상기 제2판단 수단(250)은 상기 평균기의 출력에 대하여 절대값을 구하는 절대값 계산 회로(250) : 및 상기 절대값 계산 회로의 출력 신호를 소정의 임계치와 비교하는 비교기(252)를 포함하는 타이밍 복원 시스템.2. The apparatus of claim 1, wherein the second judging means 250 compares an absolute value calculating circuit 250 for obtaining an absolute value with respect to the output of the averager, and an output signal of the absolute value calculating circuit with a predetermined threshold. A timing recovery system comprising a comparator 252. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940013288A 1994-06-14 1994-06-14 Timing recovering system KR960010856B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940013288A KR960010856B1 (en) 1994-06-14 1994-06-14 Timing recovering system

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Application Number Priority Date Filing Date Title
KR1019940013288A KR960010856B1 (en) 1994-06-14 1994-06-14 Timing recovering system

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KR960003110A true KR960003110A (en) 1996-01-26
KR960010856B1 KR960010856B1 (en) 1996-08-09

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100365928B1 (en) * 2000-07-28 2002-12-26 엘지전자 주식회사 Apparatus for real-time digital synthesization of PCM data and broadcating message in exchange system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100365928B1 (en) * 2000-07-28 2002-12-26 엘지전자 주식회사 Apparatus for real-time digital synthesization of PCM data and broadcating message in exchange system

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Publication number Publication date
KR960010856B1 (en) 1996-08-09

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