KR960002731A - Bit allocation device of multicarrier transceiver - Google Patents

Bit allocation device of multicarrier transceiver Download PDF

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KR960002731A
KR960002731A KR1019940015682A KR19940015682A KR960002731A KR 960002731 A KR960002731 A KR 960002731A KR 1019940015682 A KR1019940015682 A KR 1019940015682A KR 19940015682 A KR19940015682 A KR 19940015682A KR 960002731 A KR960002731 A KR 960002731A
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signal
noise
output
bit
bits
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KR970005594B1 (en
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임수빈
배희문
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김광호
삼성전자 주식회사
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00Arrangements affording multiple use of the transmission path
    • H04L5/0091Signaling for the administration of the divided path
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B17/00Monitoring; Testing
    • H04B17/30Monitoring; Testing of propagation channels
    • H04B17/309Measuring or estimating channel quality parameters
    • H04B17/336Signal-to-interference ratio [SIR] or carrier-to-interference ratio [CIR]

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

각 서브채널에 최적의 비트수를 할당하는 다중반송파 송수신기의에 관한 것으로서 더욱 상세하게는 비트할당 장치가 개시된다.Disclosed is a multi-carrier transceiver for assigning an optimal number of bits to each subchannel. More specifically, a bit allocation apparatus is disclosed.

본 발명에 따른 다중반송파 송수신장치의 비트할당장치는 각 서브채널별 채널응답을 평가하는 채널응답평가기; 각 서브채널별 잡음의 전력밀도를 평가하는 잡음평가기; 채널응답평가기에서 출력되는 채널응답과 잡음평가기 (169)에서 출력되는 잡음의 전력밀도를 입력하여 신호대 잡음비를 계산하는 신호태 잡음계산기; 및 신호대 잡음계산기에서 출력되는 신호대 잡음비를 입력하여 각 서브채널별 할당비트수를 조정하는 비트할당 조정기를 포함함을 특징으로 한다.The bit allocation apparatus of the multi-carrier transceiver according to the present invention includes a channel response evaluator for evaluating channel response for each subchannel; A noise evaluator for evaluating power density of noise for each subchannel; A signal type noise calculator for calculating a signal-to-noise ratio by inputting the channel response output from the channel response evaluator and the power density of the noise output from the noise evaluator 169; And a bit allocation controller for inputting a signal-to-noise ratio output from the signal-to-noise calculator to adjust the number of allocated bits for each subchannel.

본 발명에 따른 비트할당장치는 간단한 하드웨어 구성에 의해 각 서브채널에의 비트할당시 소요되는 시간을 경감시킴으로써 고속데이타 전송에 유리하다는 잇점을 갖는다.The bit allocation apparatus according to the present invention has an advantage of high speed data transmission by reducing the time required for bit allocation to each subchannel by a simple hardware configuration.

Description

다중반송파 송수신장치의 비트할당장치Bit allocation device of multicarrier transceiver

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 다중반송파 송수신기를 보이는 블럭도이다.3 is a block diagram showing a multicarrier transceiver according to the present invention.

Claims (6)

입력되는 디지탈데이타열을 서로 다른 주파수의 반송파를 갖는 복수의 서브채널에 할당 및 맵핑시키는 비트할당 및 비트맵퍼(20); 비트할당 및 비트맵퍼(20)에서 출력되는 주파수영역의 신호를 시간영역의 신호로, 변환시켜 전송채널에 제공하는 변조기(30) ; 전송채널을 통하여 수신된 시간영역의 신호를 주파수영역의 신호로 변환하는 복조기(110); 복조기(110)에서 출력되는 신호로부터 원래의 디지탈데이타열을 복원시켜 출력하는 비트역할당기 및 비트판독기(120) 그리고 상기 비트할당기 및 맵퍼(20)과 비트역할당기 및 비트판독기(120)에서의 서브채널별 비트할당을 제어하는 비트할당장치를 구비하는 다중반송파 송수신장치에 있어서, 상기 비트할당장치는 각 서브채널별 채널응답을 평가하는 채널응답평가기(150) ; 각 서브채널별 잡음의 전력밀도를 평가하는 잡음평가기(160) ; 상기 채널응답평가기(160)에서 출력되는 채널응답과 상기 잡음평가기(169)에서 출력되는 잡음의 전력밀도를 입력하여 신호대 잡음비를 계산하는 신호대 잡음계산기(170) , 및 신호대 잡음계산기(170)에서 출력되는 신호대 잡음비를 입력하여 각 서브채널별 할당비트수를 조정하는 비트할당 조정기(180)를 포함함을 특징으로 하는 다중반송파 송수신장치.A bit allocation and bitmapper 20 for allocating and mapping the input digital data sequence to a plurality of subchannels having carriers of different frequencies; A modulator 30 for converting a signal in the frequency domain output from the bit allocation and bitmapper 20 into a signal in the time domain and providing the signal to the transmission channel; A demodulator 110 for converting a signal in a time domain received through a transmission channel into a signal in a frequency domain; In the bit allocator and the bit reader 120 and the bit allocator and the mapper 20 and the bit allocator and the bit reader 120 to restore and output the original digital data sequence from the signal output from the demodulator 110 A multicarrier transceiver having a bit allocation device for controlling bit allocation for each subchannel, the bit allocation device comprising: a channel response evaluator 150 for evaluating channel response for each subchannel; A noise evaluator 160 for evaluating power density of noise for each subchannel; Signal-to-noise calculator 170 for calculating the signal-to-noise ratio by inputting the channel response output from the channel response evaluator 160 and the power density of the noise output from the noise evaluator 169, and the signal-to-noise calculator 170. And a bit allocation regulator (180) for adjusting the number of bits allocated to each subchannel by inputting a signal-to-noise ratio output from the multicarrier transceiver. 제1항에 있어서 상기 잡음평가기는 채널응답평가기(150)에서 출력되는 주파수영역의 채널응답신호를 시간영역의 채널응답신호로 변환하는 채널응답기(162) ; 채널응답기(162)에서 출력되는 시간영역의 채널응답신호를 초기화시기의 약속된 신호열과 콘볼루션연산하는 콘볼루션계산기(164) ; 콘볼루션계산기(164)의 출력과 전송채널을 통하여 수신된 시간영역의 신호를 가산하여 잡음신호를 출력하는 가산기(161) ; 및 가산기(161)에서 출력되는 잡음신호를 입력하여 잡음전력밀도를 출력하는 잡음신호 분석기(165)를 포함함을 특징으로 하는 다중반송파 송수신장치.2. The apparatus of claim 1, wherein the noise evaluator comprises: a channel responder (162) for converting a channel response signal in the frequency domain output from the channel response evaluator (150) into a channel response signal in the time domain; A convolution calculator 164 that convolutionally calculates the channel response signal in the time domain output from the channel responder 162 with a predetermined signal sequence at an initialization time; An adder 161 for adding the output of the convolution calculator 164 and a signal in the time domain received through the transmission channel to output a noise signal; And a noise signal analyzer (165) for inputting a noise signal output from the adder (161) to output a noise power density. 제2항에 있어서, 상기 잡음신호 분석기(165)는 가산기(161)에서 출력되는 잡음신호를 입력하여 반주기만큼 겹쳐지게 하는 반주기겹침기(166) ; 상기 반주기겹침기(166)의 출력으로부터 계속되는 잡음신호의 영향을 감소시키는 해밍윈도우(167) ; 잡음신호의 평균값계산과 주파수영역으로의 변환을 행하는 평균기 및 푸리에변환기(168) ; 및 상기 평균기 및 푸레에변환기(188)의 출력을 입력하고 이로부터 잡음전력밀도를 연산하여 출력하는 절대값자승기(169)를 포함함을 특징으로 하는 다중반송파 송수신장치.The apparatus of claim 2, wherein the noise signal analyzer (165) comprises: a half-cycle overlapper (166) for inputting a noise signal output from the adder (161) so as to overlap by a half cycle; A hamming window 167 for reducing the influence of the noise signal continuing from the output of the half-cycle overlapper 166; An averager and a Fourier transformer 168 for calculating an average value of the noise signal and converting it into a frequency domain; And an absolute value multiplier (169) for inputting the outputs of the averager and the Fourier transformer (188), and calculating and outputting the noise power density therefrom. 제1항에 있어서, 상기 비트할당 조정기(180)는 신호대 잡음평가기(140)에서 출력되는 신호대 잡음비를 소정의 기준값과 비교하는 비교부(182) ; 비교부(182)의 비교결과에 따라 서브채널별 비트수를 결정하여 상기 비트할당기 및 비트맵퍼(20)와 비트역할당기 및 비트판독기(120)에 제공하는 비트수결정기(183) ; 계산된 서브채널별 비트수인 b(1), b(2), ……, b(n)를 합산하여 전체비트수 BITtotal를 출력하는 덧셈기(185) ; 덧셈기(185)에서 출력되는 전체비트수(BITtotal)를 목표비트수(BITtarget)와 비교하여 전체비트수(BITtotal)가 목표비트수(BITtarget)보다 큰 경우에는 기준값 상향기 및 래치(187)의 기준값상향기를 조정하여 기준값을 상향시키고, 전체비트수(BITtotal)와 목표비트수(BITtarget)가 같아지면 래치가 동작되어 비트할당조정을 마치게 제어하는 비교기(186)를 포함함을 특징으로 하는 다중반송파 송수신장치.2. The apparatus of claim 1, wherein the bit allocation adjuster (180) comprises: a comparison unit (182) for comparing the signal-to-noise ratio output from the signal-to-noise evaluator 140 with a predetermined reference value; A bit number determiner 183 for determining the number of bits for each subchannel according to the comparison result of the comparison unit 182 and providing the number of bits to the bit allocator and the bitmapper 20 and the bit reverse allocator and the bit reader 120; B (1), b (2),... … an adder 185 for adding up b (n) to output the total number of bits BITtotal; When the total number of bits (BITtotal) output from the adder 185 is larger than the target number of bits (BITtarget), and the total number of bits (BITtotal) is larger than the target number of bits (BITtarget), the reference value of the reference value raiser and the latch 187 is used. Multi-carrier transmission / reception, comprising: a comparator 186 for adjusting the uplink to increase a reference value and controlling the latch to operate when the total bit number and the target bit number are the same. Device. 제4항에 있어서, 상기 비교부는 서브채널에 할당될 수 있는 최대비트수에 상당하는 갯수 만큼의 비교기를 설치하고, 각각의 비교기는 상기 신호대 잡음평가기(140)에서 출력되는 신호대 잡음비와 하기의 식에 의해 결정되는 기준값 REF(k)을 비교하고, 그 결과를 상기 비트수결정기에 제공함을 특징으로 하는 다중반송파 송수신장치.5. The apparatus of claim 4, wherein the comparator installs as many comparators as the maximum number of bits that can be allocated to the subchannels, and each comparator has a signal-to-noise ratio output from the signal-to-noise evaluator 140 and And a reference value REF (k) determined by an expression, and providing the result to the bit number determiner. REF(k)=(2b(k)-1)·SNRgapREF (k) = (2b (k) -1) SNRgap 여기서, k는 비트순위를 나타내는 수로서 1, 2,……, m의 값을 갖고, m은 서브채널에 할당될 수 있는 최대비트수이고, SNRgap는 허용오류확률+여유값을 나타낸다.Where k is a number representing the bit rank, 1, 2,... … , m has the value of m, m is the maximum number of bits that can be allocated to the subchannel, and SNRgap represents the allowable error probability + margin. 제4항에 있어서, 상기 비교기(188)의 비교판단결과 전체비트수(BITtotal)가 목표비트수(BITtarget)보다 작을 경우에는 허용오류확률을 만족시키기 위한 최대 데이타 전송속도를 변환시키게 하는 플랙신호를 발생하는 비트할당 에러검출기(188)를 더 구비함을 특징으로 하는 다중반송파 송수신장치.The flag signal according to claim 4, wherein the comparison result of the comparator 188 indicates that a flag signal for converting a maximum data transfer rate to satisfy an allowable error probability when the total number of bits is smaller than the target number of bits. Multi-carrier transceiver characterized in that it further comprises a bit allocation error detector (188). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940015682A 1994-06-30 1994-06-30 Bit-distribution apparatus of multi carrier transceiver KR970005594B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100379492B1 (en) * 1998-06-08 2003-05-17 엘지전자 주식회사 Power control device of mobile communication system
KR100513712B1 (en) * 2000-04-08 2005-09-07 삼성전자주식회사 power backoff method and devide thereof
KR100525932B1 (en) * 1997-10-17 2006-01-12 루센트 테크놀러지스 인크 Distribution Method and Apparatus for Multiple Carrier Pies in Wideband Code Division Multiple Access Transmission System

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100871144B1 (en) * 2002-08-10 2008-12-05 주식회사 텔콘 Arrester for base transceiver station

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100525932B1 (en) * 1997-10-17 2006-01-12 루센트 테크놀러지스 인크 Distribution Method and Apparatus for Multiple Carrier Pies in Wideband Code Division Multiple Access Transmission System
KR100379492B1 (en) * 1998-06-08 2003-05-17 엘지전자 주식회사 Power control device of mobile communication system
KR100513712B1 (en) * 2000-04-08 2005-09-07 삼성전자주식회사 power backoff method and devide thereof

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