KR950029968A - Failover Systems in Multiprocessor Systems - Google Patents
Failover Systems in Multiprocessor Systems Download PDFInfo
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- KR950029968A KR950029968A KR1019940007611A KR19940007611A KR950029968A KR 950029968 A KR950029968 A KR 950029968A KR 1019940007611 A KR1019940007611 A KR 1019940007611A KR 19940007611 A KR19940007611 A KR 19940007611A KR 950029968 A KR950029968 A KR 950029968A
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- South Korea
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- maintenance function
- module
- function block
- failure
- function blocks
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Abstract
본 발명은 다중처리모듈(노드)이 다수개 연결된 다중 프로세서 시스템에서의 장애처리를 위한 다중 프로세서 시스템에서의 장애처리 시스템에 관한 것으로, 보드의 장애감지 및 장애처리를 수행하는 다수의 유니트유지보수 기능블럭(UM); 상기 다수의 유니트유지보수 기능블럭(UM)에 접속되어 각 노드내의 장애감지 및 장애처리를 수행하는 소정 갯수의 모듈유지보수 기능블럭(MM); 상기 소정 갯수의 모듈 유지보수 기능블럭(MM)에 접속되어 시스템 전체의 장애감지 및 장애처리를 수행하는 소정의 다른 갯수의 시스템 유지보수 기능블럭(SM)을 계층적 관계를 갖도록 구성하여, 장애감지 및 장애처리 기법이 매우 단순해지며 구현이 용이해지고, 또한 시스템유지 보수기능이 이중화되어 있으므로 시스템 유지보수의 신뢰성이 높아지는 장점이 있다.The present invention relates to a failure processing system in a multiprocessor system for failure processing in a multiprocessor system in which multiple processing modules (nodes) are connected, and a plurality of unit maintenance functions for performing failure detection and failure processing of a board. Block UM; A predetermined number of module maintenance function blocks (MM) connected to the plurality of unit maintenance function blocks (UM) to perform fault detection and failure processing in each node; Connected to the predetermined number of module maintenance function blocks (MM) and configured to have a hierarchical relationship with a predetermined number of other system maintenance function blocks (SM) for performing system-wide failure detection and failure processing. And the fault handling technique is very simple, easy to implement, and the system maintenance function is duplicated, there is an advantage that the reliability of system maintenance is increased.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명이 적용되는 하드웨어 구성도, 제2도는 본 발명의 장애처리기능의 계층적 구조도, 제3도는 본 발명의 장애처리기능의 하드웨어에의 적용도.1 is a hardware configuration diagram to which the present invention is applied, FIG. 2 is a hierarchical structure diagram of the fault handling function of the present invention, and FIG. 3 is an application diagram to the hardware of the fault handling function of the present invention.
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940007611A KR950029968A (en) | 1994-04-12 | 1994-04-12 | Failover Systems in Multiprocessor Systems |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940007611A KR950029968A (en) | 1994-04-12 | 1994-04-12 | Failover Systems in Multiprocessor Systems |
Publications (1)
Publication Number | Publication Date |
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KR950029968A true KR950029968A (en) | 1995-11-24 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019940007611A KR950029968A (en) | 1994-04-12 | 1994-04-12 | Failover Systems in Multiprocessor Systems |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100395071B1 (en) * | 2001-12-20 | 2003-08-19 | 엘지전자 주식회사 | System and Method for Process Recovery in Multiprocess Operating System |
KR100440588B1 (en) * | 2002-06-10 | 2004-07-19 | 한국전자통신연구원 | Status Recognition and Alarm Device of Serial Bus Type Supporting hierarchical Structure |
-
1994
- 1994-04-12 KR KR1019940007611A patent/KR950029968A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100395071B1 (en) * | 2001-12-20 | 2003-08-19 | 엘지전자 주식회사 | System and Method for Process Recovery in Multiprocess Operating System |
KR100440588B1 (en) * | 2002-06-10 | 2004-07-19 | 한국전자통신연구원 | Status Recognition and Alarm Device of Serial Bus Type Supporting hierarchical Structure |
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