KR950025920A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- KR950025920A KR950025920A KR1019940001812A KR19940001812A KR950025920A KR 950025920 A KR950025920 A KR 950025920A KR 1019940001812 A KR1019940001812 A KR 1019940001812A KR 19940001812 A KR19940001812 A KR 19940001812A KR 950025920 A KR950025920 A KR 950025920A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- semiconductor substrate
- layer
- conductive
- conductive layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims abstract 27
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000012535 impurity Substances 0.000 claims abstract 21
- 239000000758 substrate Substances 0.000 claims abstract 18
- 239000003963 antioxidant agent Substances 0.000 claims abstract 10
- 230000003078 antioxidant effect Effects 0.000 claims abstract 10
- 230000003064 anti-oxidating effect Effects 0.000 claims abstract 7
- 238000005530 etching Methods 0.000 claims abstract 7
- 238000000137 annealing Methods 0.000 claims abstract 5
- 230000003647 oxidation Effects 0.000 claims abstract 4
- 238000007254 oxidation reaction Methods 0.000 claims abstract 4
- 230000001590 oxidative effect Effects 0.000 claims abstract 4
- 238000005468 ion implantation Methods 0.000 claims abstract 3
- 150000002500 ions Chemical class 0.000 claims 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims 2
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 2
- 229920005591 polysilicon Polymers 0.000 claims 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 2
- 238000001039 wet etching Methods 0.000 claims 2
- 238000002513 implantation Methods 0.000 claims 1
- 238000001020 plasma etching Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract 2
- 230000004888 barrier function Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/117—Oxidation, selective
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/911—Differential oxidation and etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체소자 제조방법에 관한 것으로, 고집적 반도체 직접회로에 적용이 가능한 LDD구조를 갖는 MOS트랜지스터를 제조하기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and to manufacturing a MOS transistor having an LDD structure applicable to a highly integrated semiconductor integrated circuit.
본 발명은 제1도전형의 반도체기판상에 게이트절연막을 형성하는 공정과, 상기 게이트절연막상에 게이트전극 형성을 위한 도전층을 형성하는 공정, 상기 도전층상에 산화방지층을 형성하는 공정, 상기 산화방지층상에 소정의 게이트형상을 갖는 포토레지스트패턴을 형성하는 공정, 상기 포토레지스트패턴을 마스크로 하여 상기 산화방지층을 선택적으로 식각하고 상기 도전층을 일정두께만큼 선택적으로 식각하는 공정, 상기 도전층의 노출된 부분을 선택적으로 산화하여 산화막을 형성하는 공정, 상기 산화방지층을 마스크로 하여 상기 산화막을 선택적으로 식각하는 공정, 제2도전형의 불순물을 고농도로 이온주입하여 반도체기판내의 소정영역에서 제2전도형의 고농도 불순물영역을 형성하는 공정, 상기 산화방지층 및 산화막을 제거하는 공정, 상기 제2전도형의 불순물을 저농도로 이온주입하여 반도체기판내의 소정영역에 제2도전형의 고농도 불순물영역을 형성하는 공정, 상기 산화방지층 및 산화막을 제거하는 공정, 및 산화공정 분위기 하에서 어닐링하는 공정을 포함하는 것을 특징으로 반도체소자 제조방법을 제공한다.The present invention provides a process of forming a gate insulating film on a semiconductor substrate of a first conductivity type, a process of forming a conductive layer for forming a gate electrode on the gate insulating film, a process of forming an antioxidant layer on the conductive layer, the oxidation Forming a photoresist pattern having a predetermined gate shape on the barrier layer, selectively etching the antioxidant layer using the photoresist pattern as a mask, and selectively etching the conductive layer by a predetermined thickness; Selectively oxidizing the exposed portion to form an oxide film, selectively etching the oxide film using the anti-oxidation layer as a mask, implanting impurities of a second conductivity type at a high concentration into the second region in a predetermined region of the semiconductor substrate Forming a conductive high concentration impurity region, removing the antioxidant layer and oxide film, Forming a high concentration impurity region of the second conductivity type in a predetermined region of the semiconductor substrate by ion implantation of the second conductivity type impurity at a low concentration, removing the antioxidant layer and the oxide film, and annealing under an oxidation process atmosphere It provides a semiconductor device manufacturing method comprising a.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제7도는 본 발명에 의한 LDD구조를 갖춘 MOS트랜지스터 제조방법을 도시한 공정순서도.7 is a process flowchart showing a method for manufacturing a MOS transistor having an LDD structure according to the present invention.
Claims (21)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940001812A KR0130376B1 (en) | 1994-02-01 | 1994-02-01 | Fabrication method of semiconductor device |
US08/203,896 US5427971A (en) | 1994-02-01 | 1994-03-01 | Method for fabrication of semiconductor elements |
DE4410272A DE4410272C1 (en) | 1994-02-01 | 1994-03-24 | Method for producing semiconductor elements |
JP6211733A JP2929419B2 (en) | 1994-02-01 | 1994-08-15 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940001812A KR0130376B1 (en) | 1994-02-01 | 1994-02-01 | Fabrication method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950025920A true KR950025920A (en) | 1995-09-18 |
KR0130376B1 KR0130376B1 (en) | 1998-04-06 |
Family
ID=19376587
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940001812A KR0130376B1 (en) | 1994-02-01 | 1994-02-01 | Fabrication method of semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (1) | US5427971A (en) |
JP (1) | JP2929419B2 (en) |
KR (1) | KR0130376B1 (en) |
DE (1) | DE4410272C1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100292052B1 (en) * | 1998-03-11 | 2001-09-17 | 김영환 | Method for manufacturing semiconductor device |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5830787A (en) * | 1993-03-18 | 1998-11-03 | Lg Semicon Co., Ltd. | Method for fabricating a thin film transistor |
KR970003837B1 (en) * | 1993-12-16 | 1997-03-22 | Lg Semicon Co Ltd | Fabrication of mosfet |
KR100189964B1 (en) * | 1994-05-16 | 1999-06-01 | 윤종용 | High voltage transistor and method of manufacturing the same |
US5661048A (en) * | 1995-03-21 | 1997-08-26 | Motorola, Inc. | Method of making an insulated gate semiconductor device |
JPH0923005A (en) * | 1995-07-06 | 1997-01-21 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
US5861339A (en) * | 1995-10-27 | 1999-01-19 | Integrated Device Technology, Inc. | Recessed isolation with double oxidation |
KR0175119B1 (en) * | 1995-12-06 | 1999-04-01 | 정지택 | Manufacturing Method of Recessed Channel MOSFET Using Reverse Side Wall |
JPH10125906A (en) * | 1996-10-18 | 1998-05-15 | Rohm Co Ltd | Semiconductor device and manufacture thereof |
KR100438666B1 (en) * | 1996-12-30 | 2004-10-08 | 주식회사 하이닉스반도체 | Method for manufacturing field effect transistor using photoresist spacer as ion-implantation mask of ldd structure |
US5929496A (en) * | 1997-12-18 | 1999-07-27 | Gardner; Mark I. | Method and structure for channel length reduction in insulated gate field effect transistors |
US6207485B1 (en) * | 1998-01-05 | 2001-03-27 | Advanced Micro Devices | Integration of high K spacers for dual gate oxide channel fabrication technique |
US5837588A (en) * | 1998-01-26 | 1998-11-17 | Texas Instruments-Acer Incorporated | Method for forming a semiconductor device with an inverse-T gate lightly-doped drain structure |
US6274443B1 (en) * | 1998-09-28 | 2001-08-14 | Advanced Micro Devices, Inc. | Simplified graded LDD transistor using controlled polysilicon gate profile |
US6077750A (en) * | 1998-10-27 | 2000-06-20 | Lg Semicon Co., Ltd. | Method for forming epitaxial Co self-align silicide for semiconductor device |
US6306715B1 (en) * | 2001-01-08 | 2001-10-23 | Chartered Semiconductor Manufacturing Ltd. | Method to form smaller channel with CMOS device by isotropic etching of the gate materials |
DE10146933B4 (en) * | 2001-09-24 | 2007-07-19 | Infineon Technologies Ag | Integrated spacer-array semiconductor device and method of making the same |
JP3487844B1 (en) * | 2002-06-14 | 2004-01-19 | 沖電気工業株式会社 | LDMOS type semiconductor device manufacturing method |
JP4343798B2 (en) * | 2004-08-26 | 2009-10-14 | 富士通マイクロエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP4867176B2 (en) | 2005-02-25 | 2012-02-01 | ソニー株式会社 | Manufacturing method of semiconductor device |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5418683A (en) * | 1977-07-13 | 1979-02-10 | Hitachi Ltd | Manufacture of semiconductor device |
EP0304541A1 (en) * | 1987-08-18 | 1989-03-01 | Deutsche ITT Industries GmbH | Method of making implanted wells and islands of integrated CMOS circuits |
JPH02196434A (en) * | 1989-01-26 | 1990-08-03 | Oki Electric Ind Co Ltd | Manufacture of mos transistor |
JPH02262321A (en) * | 1989-04-03 | 1990-10-25 | Toshiba Corp | Manufacture of semiconductor device |
JPH0330336A (en) * | 1989-06-27 | 1991-02-08 | Fuji Electric Co Ltd | Manufacture of semiconductor device with ldd structure |
JPH03198371A (en) * | 1989-12-27 | 1991-08-29 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
JPH0448640A (en) * | 1990-06-14 | 1992-02-18 | Oki Electric Ind Co Ltd | Manufacture of mos transistor |
JPH05152427A (en) * | 1991-11-13 | 1993-06-18 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1994
- 1994-02-01 KR KR1019940001812A patent/KR0130376B1/en not_active IP Right Cessation
- 1994-03-01 US US08/203,896 patent/US5427971A/en not_active Expired - Lifetime
- 1994-03-24 DE DE4410272A patent/DE4410272C1/en not_active Expired - Fee Related
- 1994-08-15 JP JP6211733A patent/JP2929419B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100292052B1 (en) * | 1998-03-11 | 2001-09-17 | 김영환 | Method for manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
KR0130376B1 (en) | 1998-04-06 |
JPH0864818A (en) | 1996-03-08 |
JP2929419B2 (en) | 1999-08-03 |
US5427971A (en) | 1995-06-27 |
DE4410272C1 (en) | 1995-04-06 |
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