KR950024324A - Internal power supply voltage control circuit at burn-in in semiconductor memory and its method - Google Patents

Internal power supply voltage control circuit at burn-in in semiconductor memory and its method Download PDF

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Publication number
KR950024324A
KR950024324A KR1019940001466A KR19940001466A KR950024324A KR 950024324 A KR950024324 A KR 950024324A KR 1019940001466 A KR1019940001466 A KR 1019940001466A KR 19940001466 A KR19940001466 A KR 19940001466A KR 950024324 A KR950024324 A KR 950024324A
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South Korea
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power supply
supply voltage
level
burn
internal power
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KR1019940001466A
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Korean (ko)
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KR0133260B1 (en
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김명재
조중제
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김광호
삼성전자주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

본 발명은 반도체메모리에서 특히 칩의 신뢰성 테스트를 위한 번-인시 내부전원전압의 전압레벨을 번-인레벨에 알맞도록 제어하여 신뢰성있는 번-인테스트가 이루어지도록 하는 내부전원전압 제어회로 및 그 방법에 관한 것으로, 본 발명은 일정한 정전압레벨을 가지는 기준신호와 출력신호를 래치입력하고 이들을 그 입력레벨에 응답하여 차동증폭하는 차동증폭부와, 이 차동증폭부의 출력노드와 외부전원전압단자와의 사이에 형성되어 번-인시 외부전원전압의 공급레벨을 완만하게 증가시키는 저항수단을 구비하는 내부전원전압 제어회로 및 그 방법을 개시하고 있다.The present invention provides an internal power supply voltage control circuit and method for controlling a burn-in test voltage level of a burn-in internal power supply voltage to a burn-in level, particularly for semiconductor chip reliability testing. The present invention relates to a differential amplifier which latches a reference signal and an output signal having a constant constant voltage level and differentially amplifies them in response to the input level, between the output node of the differential amplifier and an external power supply voltage terminal. An internal power supply voltage control circuit and a method are provided which are provided at the same time and have resistance means for gently increasing the supply level of the external power supply voltage at burn-in.

이와 같은 본 발명에 의한 내부전원전압 제어회로 및 그 방법은 온도의 증가 및 임계전압의 감소 등에 의해 번-인시점에서 내부전원전압의 레벨이 급격하게 증가하는 현상을 방지하여 번-인시 효과적이고도 신뢰성있는 번-인이 이루어지도록 하는 효과가 있다.The internal power supply voltage control circuit and method thereof according to the present invention prevent the phenomenon in which the level of the internal power supply voltage suddenly increases at the time of burn-in due to the increase of temperature and the decrease of the threshold voltage. This has the effect of having a burn-in.

Description

반도체메모리내에서의 번-인시 내부전원전압 제어회로 및 그 방법Internal power supply voltage control circuit at burn-in in semiconductor memory and its method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 의한 내부전원전압 제어회로의 일 실시예를 보여주는 회로도.3 is a circuit diagram showing an embodiment of an internal power supply voltage control circuit according to the present invention.

Claims (6)

내부전원전압발생회로를 가지는 반도체메모리에 있어서, 일정한 정전압레벨을 가지는 기준신호와 출력노드를 통해 래치입력되는 출력신호를 각각 입력하고 이들을 그 입력레벨에 응답하여 차동증폭하는 차동증폭부와, 상기 차동증폭부의 출력노드에 형성되는 클램핑부와, 상기 클램핑부와 외부전원전압단자와의 사이에 형성되어 번-인시 외부전원전압의 공급레벨읕 완만하게 증가시키는 저항수단을 구비함을 특징으로 하는 내부전원전압 제어회로.A semiconductor memory having an internal power supply voltage generation circuit, comprising: a differential amplifier for inputting a reference signal having a constant constant voltage level and an output signal latched through an output node, and differentially amplifying them in response to the input level; An internal power supply having a clamping part formed at an output node of the amplifying part and a resistance means formed between the clamping part and the external power supply voltage terminal to gradually increase the supply level of the external power supply voltage at burn-in. Voltage control circuit. 내부전원전압발생회로를 가지는 반도체메모리에 있어서, 일정한 정전압레벨을 가지는 기준신호와 출력노드를 통해 패치입력되는 출력신호를 각각 입력하고 이들을 그 입력레벨에 응답하여 차동증폭하는 차동증폭부와, 상기 차동증폭부의 출력노드에 형성되는 클램핑부와, 상기 차동증폭부의 출력노드와 접지전압단자와의 사이에 형성되어 번-인시 상기 기준신호의 입력레벨에 응답하여 외부전원전압의 공급레벨을 완만하게 증가시키는 번-인전압공급조절수단을 구비함을 특징으로 하는 내부전원전압 제어회로.A semiconductor memory having an internal power supply voltage generation circuit, comprising: a differential amplifier for inputting a reference signal having a constant constant voltage level and an output signal patched through an output node and differentially amplifying them in response to the input level; It is formed between the clamping portion formed on the output node of the amplifier and the output node of the differential amplifier and the ground voltage terminal to slowly increase the supply level of the external power supply voltage in response to the input level of the reference signal at burn-in. And a burn-in voltage supply adjusting means. 제2항에 있어서, 상기 번-인전압공급조절수단이, 상기 출력노드에 접속되는 다이오드트랜지스터와, 상기 기준신호를 게이트접속하고 상기 다이오드트랜지스터와 상기 접지전압단자와의 사이에 채널이 형성되는 스위칭트랜지스터로 이루어짐을 특징으로 하는 내부전원전압 제어회로.3. The switching circuit according to claim 2, wherein the burn-in voltage supply control means includes a diode transistor connected to the output node, a gate connection of the reference signal, and a channel formed between the diode transistor and the ground voltage terminal. Internal power supply voltage control circuit comprising a transistor. 내부전원전압발생회로를 가지는 반도체메모리의 내부전원전압 제어방법에 있어서, 일정한 정전압레벨을 가지는 기준신호와 출력노드를 통해 래치입력되는 출력신호를 각각 입력하고 이들을 그 입력레벨에 응답하여 차동증폭하는 차동증폭부와, 상기 차동증폭부의 출력노드에 형성되는 클램핑부와, 상기 클램핑부와 외부전원전압단자와의 사이에 형성되어 번-인시 외부전원전압의 공급레벨을 완만하게 증가시키는 저항수단을 각각 구비하여, 상기 번-인시 상기 외부전원전압의 공급레벨을 상기 저항수단을 통해 완만하게 증가시키는 동작에 응답하여 상기 내부전원전압발생회로의 출력동작을 제어함을 특징으로 하는 내부전원전압 제어방법.A method for controlling the internal power supply voltage of a semiconductor memory having an internal power supply voltage generation circuit, comprising: a differential input of a reference signal having a constant constant voltage level and an output signal latched through an output node and differentially amplifying them in response to the input level; And an amplifying section, a clamping section formed at the output node of the differential amplifier section, and resistance means formed between the clamping section and the external power supply voltage terminal to smoothly increase the supply level of the external power supply voltage at burn-in. And controlling the output operation of the internal power supply voltage generation circuit in response to the operation of gently increasing the supply level of the external power supply voltage through the resistance means at the time of burn-in. 내부전원전압발생회로를 가지는 반도체메모리의 내부전원전압 제어방법에 있어서, 일정한 정전압레벨을 가지는 기준신호와 출력노드를 통해 래치입력되는 출력신호를 각각 입력하고 이들을 그 입력레벨에 응답하여 차동증폭하는 차동증폭부와, 상기 차동증폭부의 출력노드에 형성되는 클램핑부와, 상기 차동증폭부의 출력노드와 접지전압단자와의 사이에 형성되어 번-인시 상기 기준신호의 입력레벨에 응답하여 외부전원전압의 공급레벨을 완만하게 증가시키는 번-인전압공급조절수단을 각각 구비하여, 상기 번-인시 상기 기준신호의 입력레벨에 응답하여 상기 외부전원전압의 공급레벨을 완만하게 증가시키는 동작에 응답하여 상기 내부전원전압발생회로의 출력동작을 제어함을 특징으로 하는 내부전원전압 제어방법.A method for controlling the internal power supply voltage of a semiconductor memory having an internal power supply voltage generation circuit, comprising: a differential input of a reference signal having a constant constant voltage level and an output signal latched through an output node and differentially amplifying them in response to the input level; An external power supply voltage in response to an input level of the reference signal when burned-in is formed between an amplifier part, a clamping part formed at an output node of the differential amplifier part, and an output node of the differential amplifier part and a ground voltage terminal. And a burn-in voltage supply adjusting means for slowly increasing the level, respectively, in response to the operation of slowly increasing the supply level of the external power voltage in response to the input level of the reference signal at the burn-in. An internal power supply voltage control method for controlling the output operation of the voltage generation circuit. 제5항에 있어서, 상기 번-인전압공급조절수단이, 상기 출력노드에 접속되는 다이오드트랜지스터와, 상기 기준신호를 게이트접속하고 상기 다이오드트랜지스터와 상기 접지전압단자와의 사이에 채널이 형성되는 스위칭트랜지스터로 이루어짐을 특징으로 하는 내부전원전압 제어방법.The switching circuit according to claim 5, wherein the burn-in voltage supply control means includes a diode transistor connected to the output node, a gate connection of the reference signal, and a channel formed between the diode transistor and the ground voltage terminal. Internal power supply voltage control method comprising a transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940001466A 1994-01-27 1994-01-27 Power voltage controlcircuit during burn-in at semiconductor memory KR0133260B1 (en)

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KR0133260B1 KR0133260B1 (en) 1998-04-16

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100549938B1 (en) * 1999-01-12 2006-02-07 삼성전자주식회사 Internal voltage converter of a semiconductor memory device
KR100530868B1 (en) * 1997-07-31 2006-02-09 삼성전자주식회사 Semiconductor memory device having internal supply voltage generating circuits

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000002771A (en) * 1998-06-23 2000-01-15 윤종용 Reference voltage generating circuit of a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100530868B1 (en) * 1997-07-31 2006-02-09 삼성전자주식회사 Semiconductor memory device having internal supply voltage generating circuits
KR100549938B1 (en) * 1999-01-12 2006-02-07 삼성전자주식회사 Internal voltage converter of a semiconductor memory device

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