KR950021680A - Flash Y pyrom with high coupling by increasing the surface area and its manufacturing method - Google Patents

Flash Y pyrom with high coupling by increasing the surface area and its manufacturing method Download PDF

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KR950021680A
KR950021680A KR1019930030794A KR930030794A KR950021680A KR 950021680 A KR950021680 A KR 950021680A KR 1019930030794 A KR1019930030794 A KR 1019930030794A KR 930030794 A KR930030794 A KR 930030794A KR 950021680 A KR950021680 A KR 950021680A
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insulating film
layer
film
insulating
etching
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KR1019930030794A
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KR100273684B1 (en
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최종수
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

본 발명은 반도체 기판(1)에 형성된 소오스(8)및 드레인(9); 상기 반도체기판(1)상에 형성되는 게이트 산화막(2); 상기 게이트 산화막(2)상에 형성되는 표면이 요철구조로 형성된 플로팅 게이트(7); 상기 플로팅게이트(7)상에 형성되는 층간절연막(12); 상기 층간절연막(12)상에 형성되는 조절게이트(13)를 포함하여 이루어지는 것을 특징으로 하는 표면적 증대로 높은 커플링을 갖는 플래쉬 이이피롬에 관한 것으로 실제 하부 폴리실리콘막의 면적을 넓히지 않고 표면을 사진식각함으로써 셀크기 축소에 큰 도움이 된다. 따라서 플래쉬 EPROM, EEPROM등계역에서는 프로그램 특성 향상으로 프로그래밍시 인가전압이 낮아질 수 있어 복잡한 외부회로가 감소되며 외부전력 감소도 기대할 수 있을뿐 아니라 칩의 면적 축소를 통해 생산단가가 낮아지고 공정측면에서도 낮은 전압 인가와 마진이 넓어져 소자의 품질향상 및 신뢰도를 확보할 수 있는 효과가 있다.The source and drain (9) formed in the semiconductor substrate (1); A gate oxide film 2 formed on the semiconductor substrate 1; A floating gate 7 having a surface formed on the gate oxide film 2 having an uneven structure; An interlayer insulating film 12 formed on the floating gate 7; The present invention relates to a flash Y pyrom having a high coupling due to a surface area increase, comprising a control gate 13 formed on the interlayer insulating film 12. The surface of the lower polysilicon film is photographed without increasing the area of the lower polysilicon film. Etching is a great help in reducing cell size. Therefore, in the flash EPROM, EEPROM, etc., it is possible to reduce the applied voltage when programming due to the improvement of program characteristics, which can reduce complex external circuits and reduce external power, and also reduce production costs and reduce process costs by reducing chip area. The voltage application and the margin are widened, thereby improving the quality and reliability of the device.

Description

표면적 증대로 높은 커플링을 갖는 플래쉬 이이피롬 및 그 제조방법Flash Y pyrom with high coupling by increasing the surface area and its manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 EPROM 또는 플래쉬 EEPROM셀의 단면도,3 is a cross-sectional view of an EPROM or flash EEPROM cell according to the present invention;

제4A도 내지 제4F도는 본 발명의 일실시예에 따른 플래쉬 EEPROM제조 공정도,4A to 4F are flash EEPROM manufacturing process diagram according to an embodiment of the present invention,

제5A도 내지 제5D는 본 발명의 다른 실시예에 따른 플래쉬 EEPROM제조 공정도.5A to 5D are flash EEPROM manufacturing process according to another embodiment of the present invention.

Claims (6)

표면적 증대로 높은 커플링을 갖는 플래쉬 이이피롬에 있어서, 반도체 기판(1)상에 형성된 소오스(8)및 드레인(9); 상기 반도체기판(1)상에 형성되는 게이트 산화막(2); 상기 게이트 산화막(2)상에 형성된 표면이 요철구조로 형성된 플로팅게이트(7); 상기 플로팅게이트(7)상에 형성되는 층간절연막(12); 상기 층간절연막(12)상에 형성되는 조절게이트(13)를 포함하여 이루어지는 것을 특징으로 하는 표면적 증대로 높은 커플링을 갖는 플래쉬 이이피롬.1. A flash ypyrom having a high coupling due to an increase in surface area, comprising: a source (8) and a drain (9) formed on a semiconductor substrate (1); A gate oxide film 2 formed on the semiconductor substrate 1; A floating gate 7 having a surface formed on the gate oxide film 2 having an uneven structure; An interlayer insulating film 12 formed on the floating gate 7; And a control gate 13 formed on the interlayer insulating film 12, the flash Y pyrom having a high coupling by increasing the surface area. 포면적 증대로 높은 커플링을 갖는 플래쉬 이이피롬 제조방법에 있어서, 플로팅게이트(7)표면상에 제1절연막(15)을 도포하고 상기 제1절연막(15)과 선택식각도를 갖는 제2절연막(16)을 도포하여 상기 제2절연막(16)상에 소정의 크기를 갖는 제1감광막(17)패턴을 형성하는 단계; 상기 제1감광막(17)패턴을 통해 상기 제2절연막(16)을 식각하여 제3절연막(16′)을 형상한 후에 제1감광막(17)을 제거하는 단계; 제2감광막(18)패턴을 상기 제3절연막(16′)중앙부에 형성하여 노출된 제3절연막(16′)을 식각 마스크로 제1절연막(15)을 식각하여 제4절연막(15′)을 형성하고 제2감광막(18)패턴에 노출되어 있는 제3절연막(16′)을 식각하여 제5절연막(16″)을 형성하는 단계; 제3및 제4감광막(19,20)을 사용하여 노출된 제4절연막(15′)을 식각한 후에 제3절연막(16′)을 식각함으로써 제6절연막(15″)패턴을 형성하는 단계; 상기 제6절연막(15″)패턴을 사용하여 플로팅게이트(7)를 식각하여 요철구조를 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 표면적 증대로 높은 커플링을 갖는 플래쉬 이이피롬 제조방법.In the method of manufacturing a flash Y pyrom having a high coupling by increasing the area, a first insulating film 15 is coated on the surface of the floating gate 7 and a second insulating film having a selective etching angle with the first insulating film 15. Forming a first photoresist film pattern 17 having a predetermined size on the second insulating film 16 by applying (16); Removing the first photosensitive layer (17) after the second insulating layer (16 ') is formed by etching the second insulating layer (16') through the first photosensitive layer (17) pattern; A second photoresist layer 18 pattern is formed on the center portion of the third insulation layer 16 ′, and the first insulation layer 15 is etched using the exposed third insulation layer 16 ′ as an etch mask to form the fourth insulation layer 15 ′. Forming a fifth insulating layer 16 ″ by etching the third insulating layer 16 'exposed to the second photoresist layer 18 pattern; Forming a sixth insulating film 15 ″ pattern by etching the exposed third insulating film 15 'using the third and fourth photoresist films 19 and 20, and then etching the third insulating film 16'; And forming a concave-convex structure by etching the floating gate (7) using the sixth insulating layer (15 ″) pattern. 제2항에 있어서, 상기 제1절연막(15), 제2절연막(16)은 각각 질화막, 산화막인 것을 특징으로 하는 표면적 증대로 높은 커플링을 갖는 플래쉬 이이피롬 제조방법.The method of claim 2, wherein the first insulating film (15) and the second insulating film (16) are nitride films and oxide films, respectively. 표면적 증대로 높은 커플링을 갖는 플래쉬 이이피롬 제조방법에 있어서, 플로팅게이트(7)상에 제1절연막(15)과 제2절연막(16)을 차례로 형성하고 상기 제2절연막(16)상에 제1감광막(22)을 소정의 크기로 형성하여 상기 제2절연막(16)의 중앙부를 식각하여 제3절연막(16′)을 형성하는 단계; 상기 제3절연막(16′)상에 제1절연막(15)의 소정부위를 노출시키는 제2감광막(22)을 형성하는 단계; 제2감광막(22)을 사용하여 노출된 제1절연막(15)을 식각하여 제4절연막(15′)을 형성하는 단계; 상기 제1절연막(15)의 식각 부위를 덮는 제3감광막(23)을 형성하여 제4절연막(15′)을 식각하여 제거하고, 제3절연막(16′)을 제거하여 잔류된 제5절연막(15″)패턴을 형성하는 단계; 상기 제5절연막(15″)패턴을 이용하여 플로팅게이트(7)에 요철구조를 갖도록 소정의 깊이를 식각하는 단계를 포함하여 이루어지는 것을 특징으로 하는 표면적 증대로 높은 커플링을 갖는 플래쉬 이이피롬 제조방법.In the method of manufacturing a flash Y pyrom having a high coupling by increasing the surface area, a first insulating film 15 and a second insulating film 16 are sequentially formed on the floating gate 7, and a second insulating film 16 is formed on the second insulating film 16. Forming a third insulating film 16 'by forming a first photoresist film 22 to a predetermined size to etch a central portion of the second insulating film 16; Forming a second photosensitive film (22) exposing a predetermined portion of the first insulating film (15) on the third insulating film (16 '); Etching the exposed first insulating film 15 using the second photoresist film 22 to form a fourth insulating film 15 '; A third photoresist layer 23 is formed to cover the etched portion of the first insulating layer 15, and the fourth insulating layer 15 ′ is etched and removed, and the third insulating layer 16 ′ is removed to remove the remaining fifth insulating layer ( 15 ″) forming a pattern; Etching a predetermined depth to have a concave-convex structure in the floating gate 7 by using the fifth insulating layer 15 ″ pattern. . 제4항에 있어서, 상기 제1절연막(15), 제2절연막(16)은 각각 질화막, 산화막인 것을 특징으로 하는 표면적 증대로 높은 커프링을 갖는 플래쉬 이이피롬 제조방법.The method of claim 4, wherein the first insulating film (15) and the second insulating film (16) are nitride films and oxide films, respectively. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930030794A 1993-12-29 1993-12-29 Method for manufacturing nonvolatile memory device with high coupling ratio KR100273684B1 (en)

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