KR950020614U - Input signal discrimination circuit - Google Patents
Input signal discrimination circuitInfo
- Publication number
- KR950020614U KR950020614U KR2019930032103U KR930032103U KR950020614U KR 950020614 U KR950020614 U KR 950020614U KR 2019930032103 U KR2019930032103 U KR 2019930032103U KR 930032103 U KR930032103 U KR 930032103U KR 950020614 U KR950020614 U KR 950020614U
- Authority
- KR
- South Korea
- Prior art keywords
- input signal
- discrimination circuit
- signal discrimination
- circuit
- input
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/02—Graphics controller able to handle multiple formats, e.g. input or output formats
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Synchronizing For Television (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019930032103U KR960005327Y1 (en) | 1993-12-31 | 1993-12-31 | Input-signal checking circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019930032103U KR960005327Y1 (en) | 1993-12-31 | 1993-12-31 | Input-signal checking circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950020614U true KR950020614U (en) | 1995-07-26 |
KR960005327Y1 KR960005327Y1 (en) | 1996-06-26 |
Family
ID=19375024
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019930032103U KR960005327Y1 (en) | 1993-12-31 | 1993-12-31 | Input-signal checking circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960005327Y1 (en) |
-
1993
- 1993-12-31 KR KR2019930032103U patent/KR960005327Y1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR960005327Y1 (en) | 1996-06-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
REGI | Registration of establishment | ||
FPAY | Annual fee payment |
Payment date: 20050530 Year of fee payment: 10 |
|
LAPS | Lapse due to unpaid annual fee |