KR950012708A - Semiconductor devices - Google Patents

Semiconductor devices Download PDF

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Publication number
KR950012708A
KR950012708A KR1019940026489A KR19940026489A KR950012708A KR 950012708 A KR950012708 A KR 950012708A KR 1019940026489 A KR1019940026489 A KR 1019940026489A KR 19940026489 A KR19940026489 A KR 19940026489A KR 950012708 A KR950012708 A KR 950012708A
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KR
South Korea
Prior art keywords
output
output buffer
integrated circuit
chip
circuit
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KR1019940026489A
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Korean (ko)
Inventor
마사유키 미우라
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사또오 후미오
가부시기가이샤 도시바
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Publication of KR950012708A publication Critical patent/KR950012708A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H03K17/163—Soft switching
    • H03K17/164—Soft switching using parallel switching arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명의 목적은 출력 버퍼 회로의 동시 스위칭시에 제1 및 제2전위간의 도전선에 발생하는 과도적인 전류 변화를 전원 변동 제한 수단에 의하여 제어하는데 있다.An object of the present invention is to control, by the power supply variation limiting means, a transient current change occurring in the conductive line between the first and second potentials during the simultaneous switching of the output buffer circuit.

IC 칩(10)에는 내부 데이타를 외부로 출력하기 위한 복수개의 출력 버퍼 회로(11)가 배치되고, 공통으로 전원 라인(12) 및 접지 라인(13)이 접속된다. 출력 버퍼 회로(11)의 전단에는 출력 상태 검출 회로(14)가 배치되고, 출력 버퍼 회로(11)와 병렬로 전류 제어 회로(15)가 접속된다. 16은 출력 버퍼 회로의 출력 라인(17)에 접속되는 부하 용량이다. 출력 상태 검출 회로(14)는 출력 버퍼 회로(11)에 있어서의 출력 상태, "H" 레벨 출력 및 "L" 레벨 출력의 수를 검출하고, 양자의 비율(차분)을 산출하는 연산 회로이고, 이것에 의하여 전류 제어 회로(15)가 제어된다 Vcc1은 출력 전용 전원 전위, Vss1은 출력 전용 접지 전위, Vcc2는 내부 전원 전위, Vss2는 내부 접지 전위이다.The IC chip 10 is provided with a plurality of output buffer circuits 11 for outputting internal data to the outside, and a power supply line 12 and a ground line 13 are commonly connected. An output state detection circuit 14 is arranged in front of the output buffer circuit 11, and the current control circuit 15 is connected in parallel with the output buffer circuit 11. 16 is a load capacitance connected to the output line 17 of the output buffer circuit. The output state detection circuit 14 is an arithmetic circuit that detects the number of output states, " H " level outputs and " L " level outputs in the output buffer circuit 11, and calculates the ratio (differential) between them. The current control circuit 15 is thereby controlled. Vcc1 is an output dedicated power supply potential, Vss1 is an output dedicated ground potential, Vcc2 is an internal power supply potential, and Vss2 is an internal ground potential.

Description

반도체장치Semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 제1실시예의 구성을 도시하는 회로블록도,1 is a circuit block diagram showing the construction of the first embodiment of the present invention;

제2도는 제1도 중의 일부의 구체적인 회로도.2 is a specific circuit diagram of a portion of FIG.

Claims (4)

집적 회로 내부 데이타를 칩 외부로 출력하기 위하여 집적 회로칩(10)에 내장되고, 제1 및 제2전위간의 도전선에 의하여 병렬 접속되는 복수개의 출력 버퍼 회로(11)와, 상기 각 출력 버퍼 회로의 동작 상태와, 상기 제1전위 출력인지 제2전위 출력인지를 사전에 검출하고, 그 양자의 비율(차분)에 따라서 상기 도전선의 전류량을 제어함으로써 이 출력 버퍼 회로의 동작시에 도전선에 발생되는 급격한 전류 변동 또는 전압 변동을 제어하는 전원 변동 제한 수단(14, 15)을 구비하는 것을 특징으로 하는 반도체 장치.A plurality of output buffer circuits 11 embedded in the integrated circuit chip 10 for outputting the integrated circuit internal data to the outside of the chip, and connected in parallel by conductive lines between the first and second potentials; Is detected in advance, and whether the first potential output or the second potential output is detected in advance, and the amount of current in the conductive line is controlled in accordance with the ratio (differential) thereof to generate the conductive line during operation of the output buffer circuit. And a power supply fluctuation limiting means (14, 15) for controlling abrupt current fluctuations or voltage fluctuations. 집적 회로 내부 데이타를 칩 외부로 출력하기 위하여 집적 회로 칩(10)에 내장되고, 제1 및 제2전위간의 도전선에 의하여 병렬 접속되는 복수개의 출력 버퍼 회로(11)와 ; 상기 각 출력 버퍼 회로의 동작 상태와, 제1전위 출력인지 제2전위 출력인지의 양자의 비율(차분)을 사전에 검출하는 출력 상태 검출 수단(14)과, 상기 출력 버퍼 회로와 병렬로 설치되고, 상기 출력 상태 검출 수단의 결과에 따라서 상기 도전선의 전류량을 제어함으로써 이 출력 버퍼 회로의 동작시에 도전선에 발생하는 급격한 전류 변동 또는 전압 변동을 제어하는 전류 제어 수단(15)을 구비하는 것을 특징으로 하는 반도체 장치.A plurality of output buffer circuits 11 embedded in the integrated circuit chip 10 for outputting the integrated circuit internal data to the outside of the chip and connected in parallel by conductive lines between the first and second potentials; An output state detecting means 14 for detecting in advance the ratio (differential) between the operation state of each of the output buffer circuits and whether the first potential output or the second potential output is provided, and in parallel with the output buffer circuit, And current control means (15) for controlling a sudden current change or a voltage change generated in the conductive line during operation of the output buffer circuit by controlling the amount of current in the conductive line in accordance with the result of the output state detecting means. A semiconductor device. 제2항에 있어서, 상기 출력 상태 검출 수단(14)은 상기 집적 회로 칩(10)내에서 상기 출력 버퍼 회로(11)의 전단에 설치되고 상기 도전선과는 별도의 전원을 사용하여 동작되는 것을 특징으로 하는 반도체 장치.3. The output state detecting means (14) according to claim 2, characterized in that the output state detecting means (14) is installed at the front end of the output buffer circuit (11) in the integrated circuit chip (10) and operated using a power source separate from the conductive line. A semiconductor device. 집적 회로 내부 데이타를 칩 외부로 출력히기 위하여 집적 회로 칩(10)에 내장되고, 제1 및 제 2전위간의 도전선에 의하여 병렬 접속되는 복수개의 출력 버퍼 회로(11)와, 상기 출력 버퍼 회로의 입력단에 병렬로 접속되는 상기 각 출력 버퍼 회로의 동작 상태와, 상기 제1전위 출력인지 제2전위 출력인지에 따라서 그 반대의 전위 출력을 출력하는 더미 버퍼 회로(18)를 구비하는 것을 특징으로 하는 반도체 장치.A plurality of output buffer circuits (11) embedded in the integrated circuit chip (10) for outputting the integrated circuit internal data to the outside of the chip, and connected in parallel by conductive lines between the first and second potentials; And a dummy buffer circuit 18 for outputting the opposite potential output depending on the operation state of each of the output buffer circuits connected in parallel to the input terminal and the first potential output or the second potential output. Semiconductor device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940026489A 1993-10-20 1994-10-17 Semiconductor devices KR950012708A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP93-262209 1993-10-20
JP26220993A JP3507534B2 (en) 1993-10-20 1993-10-20 Semiconductor device

Publications (1)

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KR950012708A true KR950012708A (en) 1995-05-16

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100684896B1 (en) * 2005-04-20 2007-02-20 삼성전자주식회사 Output Buffer Circuit of Semiconductor Memory Device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997009784A1 (en) * 1995-09-01 1997-03-13 Advanced Micro Devices, Inc. Output buffer incorporating shared intermediate nodes
JPWO2011024308A1 (en) * 2009-08-31 2013-01-24 パイオニア株式会社 Video signal processing apparatus, video signal processing method, and AV equipment
JP2018082328A (en) 2016-11-17 2018-05-24 東芝メモリ株式会社 Data transmission device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100684896B1 (en) * 2005-04-20 2007-02-20 삼성전자주식회사 Output Buffer Circuit of Semiconductor Memory Device

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JPH07115360A (en) 1995-05-02
JP3507534B2 (en) 2004-03-15

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