KR950007510A - Sequential Scan Converter Combined with Image Decoder - Google Patents

Sequential Scan Converter Combined with Image Decoder Download PDF

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KR950007510A
KR950007510A KR1019930016033A KR930016033A KR950007510A KR 950007510 A KR950007510 A KR 950007510A KR 1019930016033 A KR1019930016033 A KR 1019930016033A KR 930016033 A KR930016033 A KR 930016033A KR 950007510 A KR950007510 A KR 950007510A
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output
signal
sequential scan
demultiplexing
vld
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KR1019930016033A
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Korean (ko)
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KR960007206B1 (en
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이동호
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이헌조
주식회사 금성사
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Priority to KR1019930016033A priority Critical patent/KR960007206B1/en
Priority to DE69425346T priority patent/DE69425346D1/en
Priority to EP94107068A priority patent/EP0624032B1/en
Priority to US08/238,322 priority patent/US5428397A/en
Priority to CN94105360A priority patent/CN1110198C/en
Publication of KR950007510A publication Critical patent/KR950007510A/en
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Publication of KR960007206B1 publication Critical patent/KR960007206B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/12—Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

본 발명은 움직임 정보, 계수 및 매크로블럭 타입을 이용하여 순차주사식 변환장치에 관한 것으로, 입력되는 비트스트림을 의미있는 신호로 복원하고 분류하고 VLD(Variable Leng-th Decoding) 및 디멀플렉싱수단(11), 상기 VLD 및 디멀트플렉싱수단(11)으로부터 출력되는 신호를 이용하여 역양자화하는 역양자화수단(12), 상기 역양자화수단(12)으로부터 출력되고 신호를 이용하여 역양자화하는 역양자화수단(12), 상기 역양자화수단(12)으로부터 출력되고 신호를 IDCT(Invers Discrete Cosi-ne Transform)처리하는 IDCT수단(13), 상기 VLD 및 디멀티플렉싱수단(12)으로부터 출력되는 움직임 정보를 이용하여 움직임을 보상하는 제1움직임 보상수단(19), 상기 제1움직임 보상수단(19)으로부터 출력되는 신호를 가산하고 상기 제1프레임 메모리수단(18)으로 출력하는 제1가산수단(18), 상기 VLD 및 디멀티플렉싱수단(11)으로부터 출력되는 매크로블럭타입신호를 입력으로하는 제1래치수단(22), 상기 VLD 및 디멀티플렉싱수단(11)으로부터 출력되는 움직임 정보를 입력으로 하는 제2래치수단(20), 상기 IDCT수단(13)으로부터 출력되는 에러신호를 합하는 합산수단(16), 상기 합산수단(16)으로부터 출력되는 에러신호 합산치를 입력으로 하는 제3래치수단(17), 상기 제1가산수단(15)으로부터 출력되는 신호를 상기 제1, 제2 및 제3래치수단(14,20,17)으로부터 출력되는 신호를 이용하여 홀수 및 짝수필드로 나누어 각 필드를 병렬로 동시에 순차주사식 포맷으로 변환하는 제1 및 제2순차주사식 변환수단(22,23), 상기 제1및 제2순차주사식 변환수단(22,23)으로부터 출력되는 신호를 각각 저장하는 제2 및 제3프레임 메모리수단(24,25), 및 상기 제2 및 제3프레임 메모리수단(24,25)으로부터 출력되는 신호를 번갈아 가며 2배의 속도로 읽어 출력하는 제1멀티플렉싱수단(26)으로 구성된다.The present invention relates to a sequential scanning converter using motion information, coefficients, and macroblock types. The present invention reconstructs and classifies an input bitstream into a meaningful signal, and uses variable length decoding (VLD) and demultiplexing means (VLD). 11), inverse quantization means 12 for inverse quantization using a signal output from the VLD and demultiplexing means 11, inverse quantization means for outputting from the inverse quantization means 12 and inverse quantization using a signal (12) using motion information output from the inverse quantization means (12) and IDCT means (13) for processing an Invert Discrete Cosi-ne Transform (IDCT) signal, and output from the VLD and demultiplexing means (12). A first motion compensating means (19) for compensating for motion, a first adding means (18) for adding a signal output from the first motion compensating means (19), and outputting the signal to the first frame memory means (18); V First latch means 22 for inputting a macroblock type signal output from the LD and demultiplexing means 11, and second latch means for inputting motion information output from the VLD and demultiplexing means 11 ( 20), summing means 16 for summing error signals output from the IDCT means 13, third latch means 17 for inputting an error signal summed value output from the summing means 16, and the first addition; The signals output from the means (15) are divided into odd and even fields using the signals output from the first, second and third latch means (14, 20, 17). First and second sequential scan conversion means 22 and 23 and second and third frame memories for storing signals output from the first and second sequential scan conversion means 22 and 23, respectively. Means (24,25) and number of said second and third frame memories Alternating signal output from the (24, 25) consists of a first multiplexing means (26) for outputting read as twice the speed.

Description

영상디코더와 결합된 순차주사식 변환장치Sequential Scan Converter Combined with Image Decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명이 적용되는 영상디코더의 구성도,1 is a configuration diagram of an image decoder to which the present invention is applied;

제2도는 코딩을 위한 영상신호의 단위구조도,2 is a unit structure diagram of an image signal for coding;

제3도는 본 발명에 의한 순차 주사식 변환장치의 구성도,3 is a configuration diagram of a sequential scanning converter according to the present invention;

제4도는 제3도의 순차 주사식 변환부의 세부구성도,4 is a detailed configuration diagram of the sequential scanning converter of FIG.

제5도는 제4도의 각 부분의 신호파형도,5 is a signal waveform diagram of each part of FIG.

제6도는 멀티플렉서 선택 판정기준표시도,6 is a multiplexer selection criterion display,

제7도는 제4도의 보간과정을 나타낸 흐름도.7 is a flowchart showing the interpolation process of FIG.

Claims (7)

입력되는 비트스트림을 의미있는 신호로 복원하고 분류하는 VLD(Variable Leng-th Decoding) 및 디멀플렉싱수단(11), 상기 VLD 및 디멀티플렉싱수단(11)으로부터 출력되는 신호를 이용하여 역양자화하는 역양자화수단(12), 상기 역양자화수단(12)으로부터 출력되고 신호를 IDCT(Invers Discrete Cosi-ne Transform)처리하는 IDCT수단(13), 상기 VLD 및 디멀티플렉싱수단(12)으로부터 출력되는 움직임 정보를 이용하여 움직임을 보상하는 제1움직임 보상수단(19), 상기 제1움직임 보상수단(19)으로부터 출력되는 신호를 저장하는 제1프레임에 메모리수단(18), 상기 IDCT수단(13)과 제1프레임 메모리수단(18)으로부터 출력되는 신호를 가산하고 상기 제1프레임 메모리수단(18)으로 출력하는 제1가산수단(18), 상기 VLD 및 디멀티플렉싱수단(11)으로부터 출력되는 매크로블럭타입신호를 입력으로하는 제1래치수단(22), 상기 VLD 및 디멀티플렉싱수단(11)으로부터 출력되는 움직임 정보를 입력으로 하는 제2래치수단(20), 상기 IDCT수단(13)으로부터 출력되는 에러신호를 합하는 합산수단(16), 상기 합산수단(16)으로부터 출력되는 에러신호 합산치를 입력으로 하는 제3래치수단(17), 상기 제1가산수단(15)으로부터 출력되는 신호를 상기 제1, 제2 및 제3래치수단(14,20,17)으로부터 출력되는 신호를 이용하여 홀수 및 짝수필드로 나누어 각 필드를 병렬로 동시에 순차주사식 포맷으로 변환하는 제1 및 제2순차주사식 변환수단(22,23), 상기 제1및 제2순차주사식 변환수단(22,23)으로부터 출력되는 신호를 각각 저장하는 제2 및 제3프레임 메모리수단(24,25), 및 상기 제2 및 제3프레임 메모리수단(24,25)으로부터 출력되는 신호를 번갈아 가며 2배의 속도로 읽어 출력하는 제1멀티플렉싱수단(26)으로 구성되는 것을 특징으로 하는 영상디코더와 결합된 순차주사식 변환장치.Inverse quantization using the signals output from the variable length decoding (VLD) and demultiplexing means (11) and the VLD and demultiplexing means (11) for restoring and classifying the input bitstream into a meaningful signal. The motion information output from the quantization means 12, the IDCT means 13 for outputting the signal from the inverse quantization means 12, and the Invers Discrete Cosi-ne Transform (IDCT) processing, and the VLD and the demultiplexing means 12 Memory means 18, the IDCT means 13 and the first in a first frame for storing a signal output from the first motion compensation means 19, the first motion compensation means 19 to compensate for movement Adds a signal output from the frame memory means 18, and outputs a macroblock type signal output from the first addition means 18, the VLD and the demultiplexing means 11 to output to the first frame memory means 18; As input Summing means for summing the error signals output from the first latch means 22, the second latch means 20 for inputting the motion information output from the VLD and the demultiplexing means 11, and the IDCT means 13 ( 16) third latch means 17 for inputting an error signal summed value outputted from the summing means 16, and a signal output from the first adding means 15 for the first, second and third latches; First and second sequential scan conversion means (22, 23) for dividing the odd and even fields by using signals output from the means (14, 20, 17) and converting each field into a sequential scan format simultaneously in parallel; Second and third frame memory means 24 and 25 for storing signals output from the first and second sequential scan conversion means 22 and 23, and the second and third frame memory means 24, respectively. First mulch alternately reads and outputs the signal from 25) The progressive transducing device associated with the video decoder, characterized in that consisting of the flexing means (26). 제1항에 있어서, 상기 제1가산수단(15)의 출력단과 제1 및 제2순차주사식 변환수단(22,23)의 입력단에 연결되어 홀수 및 짝수필드로 나누는 디멀티플렉싱수단(21)을 더포함하여 구성되는 것을 특징으로 하는 영상디코더와 결합된 순차주사식 변환장치.2. The demultiplexing means (21) according to claim 1, further comprising a demultiplexing means (21) connected to an output end of said first adding means (15) and an input end of first and second sequential scan conversion means (22, 23) to divide into odd and even fields. And a sequential scan converter combined with an image decoder. 제1항에 있어서, 상기 제1 및 제2순차주사식 변환수단(22,23)은 매크로 블럭단위로 입력되는 신호를 라인단위로 출력하는 슬라이스 버퍼수단(42), 상기 슬라이스 버퍼수단(42)으로부터 출력되는 신호를 지연시키는 제1라인지연수단(32), 상기 제1라인지연수단(42) 및 제2라인지연수단(33)으로부터 출력되는 신호의 평균 신호를 출력하는 제2가산수단(34) 및 1/2분주수단(35), 움직임 정보를 입력으로 움직임 보상을 통해 보간하는 제2움직임보상수단(36), 에러신호 합산치와 설정된 입력으로 비교하는 비교수단(43), 상기 비교수단(43)의 출력과 매크로블럭 타입 신호를 입력으로 세가지 경우로 분류하여 제어신호를 출력하는 멀티플렉서 선택조절수단(40), 상기 1/2분주수단(35) 및 제2움직임 보상수단(36)의 출력과 전필드의 신호를 상기 멀티플렉서 선택조절수단(40)의 제어신호에 다라 선택하여 출력하는 제2멀티플렉싱수단(39), 및 상기 제2멀티플렉싱수단(39)과 제1라인지연수단(33)의 출력을 번갈아 선택하여 출력하는 제3멀티플렉싱수단(41)으로 구성되는 것을 특징으로 하는 영상디코더와 결합된 순차주사식 변환장치.The method of claim 1, wherein the first and second sequential scan conversion means (22, 23) is a slice buffer means 42 for outputting a signal input in units of macro blocks in line units, the slice buffer means 42 Second addition means (34) for outputting an average signal of signals output from the first line delay means (32), the first line delay means (42), and the second line delay means (33) for delaying the signal output from the first line delay means (32). And 1/2 dividing means 35, second motion compensation means 36 for interpolating motion information through motion compensation as input, comparing means 43 for comparing the error signal sum with a set input, and the comparing means. The multiplexer selection adjusting means 40, the 1/2 dividing means 35, and the second motion compensating means 36 which classify the output of the 43 and the macroblock type signal into three cases and output the control signal. Output and the signal of all the fields of the multiplexer selection control means 40 The second multiplexing means 39 for selecting and outputting the signal according to the fish signal, and the third multiplexing means 41 for alternately selecting and outputting the outputs of the second multiplexing means 39 and the first line delay means 33. A sequential scan converter combined with an image decoder, characterized in that it is configured. 제3항에 있어서, 상기 멀티플렉서 선택조절수단(40)은 에러신호 합산치가 설정된 임계치보다 작고 매크로블럭 타입이 인트라 프레임모드이거나 상기 에러신호 합산치가 설정된 임계치보다 큰 경우, 상기 에러신호 합산치가 설정임계치보다 작고 상기 매크로블럭 타입이 모션 컴펜세이티드모드인 경우, 및 상기 에러신호 합산치가 설정 임계치보다 작고 매크로블럭 타입인 논 모션 컴펜세이티드 인터프레임인 경우로 나누어 제어신호를 출력하는 것을 특징으로 하는 영상디코더와 결합된 순차주사식 변환장치.4. The multiplexer selection adjusting means (40) according to claim 3, wherein the multiplexer selection adjusting means (40) is smaller than the set threshold when the error signal sum is smaller than the set threshold and the macroblock type is the intra frame mode or the sum of the error signal is greater than the set threshold. And a control signal is output when the macroblock type is a motion-competed mode and the sum of the error signal is less than a predetermined threshold and the non-blocking interframe is a macroblock type. Sequential scan inverter combined with 제4항에 있어서, 상기 멀티플렉서 선택조절수단(40)은, 상기 에러신호 합산치가 설정된 임계치보다 작고 매크로블럭타입이 인트라 프레임 모드이거나 상기 에러신호 합산치가 설정된 임계치보다 큰 경우에는 상기 제2멀티플렉싱수단(39)이 상기 1/2분주수단(35)의 출력을 선택하도록 하는 것을 특징으로 하는 영상디코더와 결합된 순차주사식 변환장치.The method of claim 4, wherein the multiplexer selection adjusting means (40) includes the second multiplexing means when the error signal sum is smaller than the set threshold and the macroblock type is the intra frame mode or the error signal sum is greater than the set threshold. 39. A sequential scan converter combined with an image decoder, characterized in that 39) selects the output of the 1/2 dividing means (35). 제4항에 있어서, 상기 멀티플렉서 선택조절수단(40)은, 상기 에러신호 합산치가 설정된 임계치보다 작고 매크로블럭타입이 모션 컴펜세이트도 모드인 경우 상기 제2멀티플렉싱수단(39)이 상기 움직임 보상수단(36)의 출력을 선택하도록 하는 것을 특징으로 하는 영상디코더와 결합된 순차주사식 변환장치.5. The method of claim 4, wherein the multiplexer selection adjusting means (40) is configured such that the second multiplexing means (39) is the motion compensating means when the sum of the error signal values is smaller than the set threshold and the macroblock type is in the motion compendium mode. 36. A sequential scan converter combined with an image decoder, characterized in that the output is selected. 제4항에 있어서, 상기 멀티플렉서 선택조절수단(40)은, 상기 에러신호 합산치가 설정된 임계치보다 작고 매크로블럭타입이 논 모션 컴펜세이트도 인터 프레임모드인 경우 상기 전 필드의 신호를 선택하도록 하는 것을 특징으로 하는 영상디코더와 결합된 순차주사식 변환장치.5. The multiplexer selection adjusting means (40) according to claim 4, wherein the multiplexer selection adjusting means (40) selects the signals of all the fields when the sum of the error signal values is smaller than the set threshold and the macroblock type is the non-motion compensate. Sequential scan converters combined with video decoders. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930016033A 1993-05-07 1993-08-18 Progressive scan conversion device combined with video decoder KR960007206B1 (en)

Priority Applications (5)

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KR1019930016033A KR960007206B1 (en) 1993-08-18 1993-08-18 Progressive scan conversion device combined with video decoder
DE69425346T DE69425346D1 (en) 1993-05-07 1994-05-05 Method and device for converting video formats
EP94107068A EP0624032B1 (en) 1993-05-07 1994-05-05 Video format conversion apparatus and method
US08/238,322 US5428397A (en) 1993-05-07 1994-05-05 Video format conversion apparatus for converting interlaced video format into progressive video format using motion-compensation
CN94105360A CN1110198C (en) 1993-05-07 1994-05-07 Video format conversion apparatus and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930016033A KR960007206B1 (en) 1993-08-18 1993-08-18 Progressive scan conversion device combined with video decoder

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KR950007510A true KR950007510A (en) 1995-03-21
KR960007206B1 KR960007206B1 (en) 1996-05-29

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KR1019930016033A KR960007206B1 (en) 1993-05-07 1993-08-18 Progressive scan conversion device combined with video decoder

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100250679B1 (en) * 1996-12-27 2000-04-01 전주범 Interlace scaning converting apparatus for projector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100250679B1 (en) * 1996-12-27 2000-04-01 전주범 Interlace scaning converting apparatus for projector

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KR960007206B1 (en) 1996-05-29

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