KR950007129A - Flash memory and its manufacturing method - Google Patents

Flash memory and its manufacturing method Download PDF

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Publication number
KR950007129A
KR950007129A KR1019930015543A KR930015543A KR950007129A KR 950007129 A KR950007129 A KR 950007129A KR 1019930015543 A KR1019930015543 A KR 1019930015543A KR 930015543 A KR930015543 A KR 930015543A KR 950007129 A KR950007129 A KR 950007129A
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South Korea
Prior art keywords
oxide film
semiconductor substrate
gate
forming
trench
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KR1019930015543A
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Korean (ko)
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최종수
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김주용
현대전자산업 주식회사
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Priority to KR1019930015543A priority Critical patent/KR950007129A/en
Publication of KR950007129A publication Critical patent/KR950007129A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)

Abstract

본 발명은 플레쉬 메모리 및 그 제조방법에 관한 것으로서, 반도체 기판에 일정간격으로 트랜치들을 형성하고, 상기 반도체 기판의 상·하측 표면에 소오스 및 드레인을 형성한 후, 게이트 산화막을 전표면에 형성한다. 그 다음 상기 트랜치의 측벽에 스페이서 형상의 플루팅 게이트를 형성하고, 상기 플루팅 게이트의 표면에 층간 산하막을 형성한 후, 상기 층간 산화막 및 게이트 산화막 상에 컨트롤 게이트를 형성한다. 이러한 방법으로 제조된 플레쉬 메모리는 플루팅 게이트의 측면 및 밑면의 터날산화막을 통하여 프로그램 및 소거가 진행되므로, 펀치스루 전압이 높아지고, 프로그램 효율이 증가되며, 소오스 및 드레인 하부에 형성되어 있는 선택채널에 의해 문턱전압이 조절되므로 과잉소거가 방지되고, 반도체 기판의 상하측에 형성되므로 플레시 메모리의 고집적화가 가능하다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory and a method of manufacturing the same, wherein trenches are formed on a semiconductor substrate at regular intervals, and sources and drains are formed on upper and lower surfaces of the semiconductor substrate, and then gate oxides are formed on the entire surface. Next, a spacer-shaped fluting gate is formed on the sidewalls of the trench, an interlayer film is formed on the surface of the fluting gate, and then a control gate is formed on the interlayer oxide film and the gate oxide film. The flash memory fabricated in this manner is programmed and erased through tunnel oxides on the side and bottom of the fluting gate, so that the punch-through voltage is increased, the program efficiency is increased, and the select memory is formed in the select channel formed under the source and drain. The threshold voltage is adjusted to prevent over-erasing, and is formed on the upper and lower sides of the semiconductor substrate, thereby enabling high integration of the flash memory.

Description

플레쉬 메모리 및 그 제조방법Flash memory and its manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 플레쉬 메모리의 레이 아웃도,3 is a layout diagram of a flash memory according to the present invention;

제4도는 본 발명에 따른 플레쉬 메모리를 제조하되 제3도에서의 선 Ⅳ-Ⅳ에 따라 도시한 단면 사시도,FIG. 4 is a cross-sectional perspective view of a flash memory according to the present invention, but taken along line IV-IV of FIG. 3;

제5도 (A)~(D)는 본 발명에 따른 플레쉬 메모리의 제조 공정도.5A to 5D are manufacturing process diagrams of the flash memory according to the present invention.

Claims (7)

플레쉬 메모리에 있어서, 제1도전형의 반도체 기판 상에 일정간격으로 형성된 트랜치들과, 상기 트랜치들 저면의 반도체기판으로 제2도전형의 불순물을 이온주입하여 형성된 드레인들과, 상기 반도체 기판의 상측 표면으로 제2도전형의 불순몰을 이온주입하여 형성된 소오스들과, 상기 트랜치의 표면 및 반도체 기판 상부면에 형성된 게이트 산화막과, 상기 트랜치 측벽의 게이트 산화막 상에 스페이서 형상으로 형성된 플루팅 게이트들과, 상기 플루팅 게이트 표면에 형성된 층간 산화막과, 상기 소오스와 드레인 및 플루팅 게이트와 중첩되도록 상기 게이트 산화막과 층간 산화막상에 형성된 컨트롤 게이트를 구비하여 되는 플레쉬 메모리.A flash memory comprising: trenches formed on a semiconductor substrate of a first conductivity type at intervals, drains formed by ion implantation of impurities of a second conductivity type into a semiconductor substrate on a bottom surface of the trenches, and an upper side of the semiconductor substrate; Sources formed by ion implanting impurity of the second conductivity type into the surface, Gate oxide film formed on the surface of the trench and the upper surface of the semiconductor substrate, Fluting gates formed in a spacer shape on the gate oxide film of the trench sidewalls; And an interlayer oxide film formed on the surface of the fluting gate, and a control gate formed on the gate oxide film and the interlayer oxide film so as to overlap the source, drain, and fluting gate. 제1항에 있어서, 상기 제1 및 제2도전형이 서로 다른 도전형인 것을 특징으로 하는 플레쉬 메모리.The flash memory of claim 1, wherein the first and second conductivity types are different conductivity types. 제1항에 있어서, 상기 폴리스페이서와 접하는 제1산화막이 타널산화막이 되는 플레쉬 메모리.The flash memory of claim 1, wherein the first oxide film in contact with the police spacer is a channel oxide film. 플레쉬 메모리의 제조방법에 있어서, 제1도전형의 반도체 기판에 일정간격으로 트랜치들을 형성하는 단계와, 상기 트랜치 및 반도체 기판상에 희생 산화막을 형성하는 단계와, 상기 구조의 전표면에 제2도전형의 불순물 이온을 이온주입하여 상기 트랜치 저부의 반도체 기판과 반도체 기판의 최상부에 드레인 및 소오스를 각각 형성하는 단계와, 상기 희생 산화막을 제거한 후 상기 트랜치의 표면 및 반도체 기판 상부면에 게이트 산화막을 형성하는 단계와, 상기 트랜치 양측벽의 제1산화막 상에 스페이서 형상의 플루팅 게이트들을 형성하는 단계와, 상기 소오스 및 드레인 하부의 반도체 기판으로 제1도전형의 불순물을 이온주입하여 문턱전압 조절을 위한 선택채널을 형성하는 단계와, 상기 플루팅 게이트 상에 층간산화막을 형성하는 단계와, 상기 층간산화막 및 게이트 산화막상에 폴리 실리콘층을 도포한 후 사진식각하여 컨트롤 게이트를 형성하는 단계를 포함하는 플레쉬 메모리 제조방법.A method of manufacturing a flash memory, the method comprising: forming trenches at a predetermined interval on a first conductive semiconductor substrate, forming a sacrificial oxide film on the trench and the semiconductor substrate, and forming a second conductive layer on the entire surface of the structure. Implanting impurity ions into the semiconductor substrate at the bottom of the trench and forming a drain and a source at the top of the semiconductor substrate; and removing the sacrificial oxide film and forming a gate oxide film on the trench surface and the upper surface of the semiconductor substrate. Forming a spacer-shaped fluting gates on the first oxide film on both sidewalls of the trench, and implanting impurities of a first conductivity type into the semiconductor substrate under the source and drain to adjust the threshold voltage. Forming a select channel, forming an interlayer oxide film on the fluting gate, Between the flash memory production method comprising a step of forming a gate oxide film and the control gate by a photolithography and then applying a layer of polysilicon on the oxide film. 제4항에 있어서, 상기 제1 및 제2도전형이 서로 반대 도전형인 것을 특징으로 하는 플레쉬 메모리의 제조방법.The method of claim 4, wherein the first and second conductive types are opposite conductive types. 제4항에 있어서, 상기 플루팅 게이트는 게이트 산화막 상에 폴리 실리콘층을 형성한 후, 폴리 실리콘층을 이방성식각하여 트랜치 측벽에만 폴리 실리콘을 남겨 형성하는 것을 특징으로 하는 플레쉬 메모리의 제조방법.5. The method of claim 4, wherein the fluting gate forms a polysilicon layer on the gate oxide layer and then anisotropically etches the polysilicon layer to leave polysilicon only on the trench sidewalls. 6. 제4항에 있어서, 상기 소오스 및 드레인과 선택채널을 형성하기 위한 이온주입을 상기 반도체 기판에 수직하게 실시하여, 상기 트랜치의 측벽으로 이온주입이 되진 않도록 하는 플레쉬 메모리의 제조방법.The method of claim 4, wherein ion implantation for forming the source and drain and the select channel is performed perpendicular to the semiconductor substrate to prevent ion implantation into sidewalls of the trench. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930015543A 1993-08-11 1993-08-11 Flash memory and its manufacturing method KR950007129A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100439190B1 (en) * 2001-12-20 2004-07-07 동부전자 주식회사 Flash eeprom and method for fabricating the same
KR100424189B1 (en) * 1998-12-04 2004-09-18 주식회사 하이닉스반도체 Flash memory cell
KR100683204B1 (en) * 2005-12-13 2007-02-15 현대모비스 주식회사 Glove box for a automobile
KR100934790B1 (en) * 2007-09-07 2009-12-31 주식회사 동부하이텍 DMOS transistor and manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100424189B1 (en) * 1998-12-04 2004-09-18 주식회사 하이닉스반도체 Flash memory cell
KR100439190B1 (en) * 2001-12-20 2004-07-07 동부전자 주식회사 Flash eeprom and method for fabricating the same
KR100683204B1 (en) * 2005-12-13 2007-02-15 현대모비스 주식회사 Glove box for a automobile
KR100934790B1 (en) * 2007-09-07 2009-12-31 주식회사 동부하이텍 DMOS transistor and manufacturing method

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