KR950007129A - Flash memory and its manufacturing method - Google Patents
Flash memory and its manufacturing method Download PDFInfo
- Publication number
- KR950007129A KR950007129A KR1019930015543A KR930015543A KR950007129A KR 950007129 A KR950007129 A KR 950007129A KR 1019930015543 A KR1019930015543 A KR 1019930015543A KR 930015543 A KR930015543 A KR 930015543A KR 950007129 A KR950007129 A KR 950007129A
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- semiconductor substrate
- gate
- forming
- trench
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract 14
- 239000000758 substrate Substances 0.000 claims abstract 14
- 239000011229 interlayer Substances 0.000 claims abstract 5
- 239000010410 layer Substances 0.000 claims 5
- 239000012535 impurity Substances 0.000 claims 4
- 238000000034 method Methods 0.000 claims 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 4
- 229920005591 polysilicon Polymers 0.000 claims 4
- 238000005468 ion implantation Methods 0.000 claims 3
- 150000002500 ions Chemical class 0.000 claims 2
- 125000006850 spacer group Chemical group 0.000 claims 2
- 238000000206 photolithography Methods 0.000 claims 1
- 230000002265 prevention Effects 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
Abstract
본 발명은 플레쉬 메모리 및 그 제조방법에 관한 것으로서, 반도체 기판에 일정간격으로 트랜치들을 형성하고, 상기 반도체 기판의 상·하측 표면에 소오스 및 드레인을 형성한 후, 게이트 산화막을 전표면에 형성한다. 그 다음 상기 트랜치의 측벽에 스페이서 형상의 플루팅 게이트를 형성하고, 상기 플루팅 게이트의 표면에 층간 산하막을 형성한 후, 상기 층간 산화막 및 게이트 산화막 상에 컨트롤 게이트를 형성한다. 이러한 방법으로 제조된 플레쉬 메모리는 플루팅 게이트의 측면 및 밑면의 터날산화막을 통하여 프로그램 및 소거가 진행되므로, 펀치스루 전압이 높아지고, 프로그램 효율이 증가되며, 소오스 및 드레인 하부에 형성되어 있는 선택채널에 의해 문턱전압이 조절되므로 과잉소거가 방지되고, 반도체 기판의 상하측에 형성되므로 플레시 메모리의 고집적화가 가능하다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory and a method of manufacturing the same, wherein trenches are formed on a semiconductor substrate at regular intervals, and sources and drains are formed on upper and lower surfaces of the semiconductor substrate, and then gate oxides are formed on the entire surface. Next, a spacer-shaped fluting gate is formed on the sidewalls of the trench, an interlayer film is formed on the surface of the fluting gate, and then a control gate is formed on the interlayer oxide film and the gate oxide film. The flash memory fabricated in this manner is programmed and erased through tunnel oxides on the side and bottom of the fluting gate, so that the punch-through voltage is increased, the program efficiency is increased, and the select memory is formed in the select channel formed under the source and drain. The threshold voltage is adjusted to prevent over-erasing, and is formed on the upper and lower sides of the semiconductor substrate, thereby enabling high integration of the flash memory.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 본 발명에 따른 플레쉬 메모리의 레이 아웃도,3 is a layout diagram of a flash memory according to the present invention;
제4도는 본 발명에 따른 플레쉬 메모리를 제조하되 제3도에서의 선 Ⅳ-Ⅳ에 따라 도시한 단면 사시도,FIG. 4 is a cross-sectional perspective view of a flash memory according to the present invention, but taken along line IV-IV of FIG. 3;
제5도 (A)~(D)는 본 발명에 따른 플레쉬 메모리의 제조 공정도.5A to 5D are manufacturing process diagrams of the flash memory according to the present invention.
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930015543A KR950007129A (en) | 1993-08-11 | 1993-08-11 | Flash memory and its manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930015543A KR950007129A (en) | 1993-08-11 | 1993-08-11 | Flash memory and its manufacturing method |
Publications (1)
Publication Number | Publication Date |
---|---|
KR950007129A true KR950007129A (en) | 1995-03-21 |
Family
ID=66817601
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930015543A KR950007129A (en) | 1993-08-11 | 1993-08-11 | Flash memory and its manufacturing method |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950007129A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100439190B1 (en) * | 2001-12-20 | 2004-07-07 | 동부전자 주식회사 | Flash eeprom and method for fabricating the same |
KR100424189B1 (en) * | 1998-12-04 | 2004-09-18 | 주식회사 하이닉스반도체 | Flash memory cell |
KR100683204B1 (en) * | 2005-12-13 | 2007-02-15 | 현대모비스 주식회사 | Glove box for a automobile |
KR100934790B1 (en) * | 2007-09-07 | 2009-12-31 | 주식회사 동부하이텍 | DMOS transistor and manufacturing method |
-
1993
- 1993-08-11 KR KR1019930015543A patent/KR950007129A/en not_active Application Discontinuation
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100424189B1 (en) * | 1998-12-04 | 2004-09-18 | 주식회사 하이닉스반도체 | Flash memory cell |
KR100439190B1 (en) * | 2001-12-20 | 2004-07-07 | 동부전자 주식회사 | Flash eeprom and method for fabricating the same |
KR100683204B1 (en) * | 2005-12-13 | 2007-02-15 | 현대모비스 주식회사 | Glove box for a automobile |
KR100934790B1 (en) * | 2007-09-07 | 2009-12-31 | 주식회사 동부하이텍 | DMOS transistor and manufacturing method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR960032761A (en) | Semiconductor device, method of manufacturing semiconductor device, split gate type transistor, method of manufacturing split gate type transistor, and nonvolatile semiconductor memory | |
KR960036090A (en) | Flash Y pyrom cell and manufacturing method thereof | |
KR100295685B1 (en) | Semiconductor memory device and fabricating method thereof | |
KR960006046A (en) | Manufacturing method of fresh E.P.Rom | |
KR970008624A (en) | Flash memory device and manufacturing method thereof | |
US6903405B2 (en) | Semiconductor memory device with a pair of floating gates | |
KR950007129A (en) | Flash memory and its manufacturing method | |
KR970054236A (en) | Flash memory device and manufacturing method thereof | |
KR100554833B1 (en) | Nonvolatile memory device and method for manufacturing the same | |
KR20050055223A (en) | High voltage transistor in semiconductor device | |
KR960006045A (en) | Manufacturing Method of Semiconductor Device | |
KR100210857B1 (en) | Non-volatile semiconductor memory and its manufacturing method | |
KR950011030B1 (en) | Making method eeprom | |
KR970013338A (en) | Nonvolatile Memory Device and Manufacturing Method Thereof | |
KR960006051A (en) | Flash Y pyrom cell and manufacturing method thereof | |
KR100277900B1 (en) | Nonvolatile Memory Cells and Manufacturing Method Thereof | |
KR100277885B1 (en) | Nonvolatile memory device and method for fabricating the same | |
KR100246350B1 (en) | Plash eeprom and manufacturing method thereof | |
JPS5924548B2 (en) | Method for manufacturing semiconductor memory device | |
KR100383764B1 (en) | Method for manufacturing flash memory cell | |
KR0124648B1 (en) | Flash eprom cell | |
KR100264072B1 (en) | Flash memory and manufacturing method thereof | |
KR960006050A (en) | Flash Y pyrom cell and manufacturing method thereof | |
KR960012498A (en) | Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof | |
KR980005422A (en) | Method for manufacturing semiconductor device and its structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |