KR950005493B1 - Method for manufacturing of semiconductor package - Google Patents

Method for manufacturing of semiconductor package Download PDF

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Publication number
KR950005493B1
KR950005493B1 KR1019910025347A KR910025347A KR950005493B1 KR 950005493 B1 KR950005493 B1 KR 950005493B1 KR 1019910025347 A KR1019910025347 A KR 1019910025347A KR 910025347 A KR910025347 A KR 910025347A KR 950005493 B1 KR950005493 B1 KR 950005493B1
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KR
South Korea
Prior art keywords
chip
board
pad
semiconductor package
flexible circuit
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KR1019910025347A
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Korean (ko)
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KR930015147A (en
Inventor
김구성
안승호
Original Assignee
삼성전자주식회사
김광호
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Application filed by 삼성전자주식회사, 김광호 filed Critical 삼성전자주식회사
Priority to KR1019910025347A priority Critical patent/KR950005493B1/en
Publication of KR930015147A publication Critical patent/KR930015147A/en
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Publication of KR950005493B1 publication Critical patent/KR950005493B1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits

Abstract

The semiconductor package manufacturing method comprises the steps of: connecting a chip pad on a chip and a board pad of a multi-layered flexible circuit board by using an adhesive; arranging a reed in the form that the metal line of each board pad is arranged in one direction; bonding the bonded boards of the chip by the adhesive; polishing the chip and multi-layered flexible circuit board to expose the reed; and connecting the exposed reed to a substrate by using the adhesive.

Description

반도체 패키지 제조방법Semiconductor Package Manufacturing Method

제1도는 본 발명에 있어서 칩을 보드에 접착한 상태를 나타낸 도면.1 is a view showing a state in which the chip is bonded to the board in the present invention.

제2도는 제1도의 칩이 접착된 보드의 전체구조도.2 is an overall structure diagram of a board to which the chips of FIG. 1 are bonded.

제3도(a)도는 제2도의 형성물을 적층한 상태를 나타낸 도면.FIG. 3 (a) shows a state in which the formations of FIG. 2 are stacked.

제3도(b)는 제3도(a)를 기판상에 실장한 본 발명 반도체 패키지의 구조도이다.FIG. 3B is a structural diagram of the semiconductor package of the present invention in which FIG. 3A is mounted on a substrate.

본 발명은 반도체 패키지에 관한 것으로, 특히 칩상의 본딩패드를 다층 유연성 회로 보드(multilayer flexible circuit board)를 사용하여 상호 연결시키는 반도체 패키지 제조방법에 관한 것이다. 고밀도 패키지에 있어서 3차원 패키징기법은 차세대 패키지 분야에서 가장 유망한 분야로 주목되고 있는 바 종래의 패키지에 있어서 칩들간의 상호 연결방법으로는 테이프의 리드와 칩의 전극 패드 사이에 Au범프(bump)를 개입하여 칩과 패턴간의 전기적 연결을 이루는 TAB(Tape Automatic Bonding)방식이나 칩 표면에 금속배선으로 전기적인 패스를 만들고 폴리싱(polishing)한 후 각 패드부분에 범핑을 형성하여 연결하는 방법을 쓰고 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to a method of manufacturing a semiconductor package in which bonding pads on a chip are interconnected using a multilayer flexible circuit board. In the high density package, the 3D packaging technique is attracting attention as the most promising field in the next generation packaging field. In the conventional package, the interconnection between the chips is performed by using Au bumps between the lead of the tape and the electrode pad of the chip. TAB (Tape Automatic Bonding), which makes the electrical connection between the chip and the pattern, or a metal path on the surface of the chip is made and polished, and then the bumps are formed on each pad.

즉, 칩 표면의 하측 한 부분으로 각 패드들의 상호연결선을 금속배선 처리하여 적층한 다음 그 면을 폴리싱 한 후 범핑하여 보드에 연결하거나 TAB을 사용하여 하측 한 부분에 TAB내부 패스라인을 만들어 동일한 방법으로 패키징한다.In other words, the interconnection of each pad is laminated to the lower part of the chip surface by metal wiring, then polished and bumped to connect to the board, or the TAB inner pass line is made on the lower part by using TAB. Package it as

이와 같은 종래의 반도체 패키징 방법은 칩 표면에 금속배선패턴을 만들거나 고가의 범프를 형성하여야 하는 문제점이 있다.Such a conventional semiconductor packaging method has a problem in that metal wiring patterns or expensive bumps must be formed on the chip surface.

따라서, 본 발명은 이와 같은 종래 반도체 패키지의 문제점을 해결하기 위해 발명한 것으로, 칩간의 상호 연결이 쉽고 안정되며 전기적 파라메타의 조절이 쉬운 반도체 패키지의 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to solve the problems of the conventional semiconductor package, and an object of the present invention is to provide a method of manufacturing a semiconductor package in which interconnections between chips are easy and stable, and electrical parameters are easily controlled.

상기한 목적을 달성하기 위한 본 발명은 칩 패드가 부착된 다층 유연성 회로 보드(multilayer flexible circuit board)의 메탈라인을 한 면으로 규칙적으로 배열시켜 적층하여 기판에 실장시키는 것을 특징으로 한다.The present invention for achieving the above object is characterized in that the metal lines of the multilayer flexible circuit board (multilayer flexible circuit board) to which the chip pad is attached regularly arranged on one side, stacked and mounted on the substrate.

이하, 본 발명을 첨부한 도면을 참조하여 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings of the present invention will be described in detail.

제1도는 본 발명 반도체 패키지에 있어서 칩을 보드에 접착한 상태를 나타낸 도면이다.1 is a view showing a state in which a chip is bonded to a board in the semiconductor package of the present invention.

칩(1)의 칩 패드(2)와 다층 유연성 회로 보드(3)의 보드패드(4)를 구형의 금속 충전제(5)가 첨가된 이방성도전 필름이나 페이스트(paste;6)를 사용하여 플립칩 형태로 접착한다.The chip pad 2 of the chip 1 and the board pad 4 of the multi-layer flexible circuit board 3 are flip-chips using an anisotropic conductive film or paste with a spherical metal filler 5 added thereto. Bond in the form.

이때 보드패드(4)는 칩 패드(2)의 부위에 접착되도록 하되 Au,Ag 또는 솔더로 도금처리한다. 이러한 공정을 반복하여 칩(1)이 보드(3)상에 접착된 적층형의 패키지를 다수 형성하고, 제2도에 도시한 바와 같이 보드(3)의 메탈라인(7)은 보드패드(4)에서 시작하여 보드(3)의 한 면으로 규칙적으로 리드(8)를 배열한 다음, 제3도(a)와 같이 이방성도전 페이스트(6)로 접착된 칩(1)과 보드(3)를 접착제(9)로 서로 어탯치시켜 접착시킨다. 이때 칩(1)이 부착된 보드(3)의 각 리드(8)는 도시된 바와 같이 한 방향이 되도록 배열시킨다.At this time, the board pad 4 is bonded to the portion of the chip pad 2, but plated with Au, Ag or solder. This process is repeated to form a plurality of stacked packages in which the chip 1 is bonded onto the board 3, and as shown in FIG. 2, the metal lines 7 of the board 3 are connected to the board pad 4. Arrange the leads 8 regularly on one side of the board 3, starting at, and then glue the board 1 and the chip 1 bonded with the anisotropic conductive paste 6 as shown in FIG. Attach to each other by attaching (9). At this time, each lead 8 of the board 3 to which the chip 1 is attached is arranged in one direction as shown.

이후 서로 부착된 보드의 일면을 폴리싱하여 배열된 리드(8)를 노출시킨 후 제3도(b)와 같이 이방성도전필름이나 페이스트(6)를 사용하여 전기적으로 접속되도록 제작한 패키지의 리드 부분을 기판(10)상에 붙여 소자를 완성시킨다.Thereafter, one side of the boards attached to each other is polished to expose the arranged leads 8, and then the lead portions of the package manufactured to be electrically connected using an anisotropic conductive film or paste 6 as shown in FIG. It attaches on the board | substrate 10, and completes an element.

본 발명에 의한 반도체 패키지 제조방법은 보드상에 접지층으로 만들 수 있고, 칩과 보드간 및 보드와 기판 접착시 저온 연결이 가능하며 PCB패턴간 라인의 길이가 짧아짐으로 전기적인 성능을 향상시킬수 있다.The semiconductor package manufacturing method according to the present invention can be made as a ground layer on the board, low-temperature connection between the chip and the board and when bonding the board and the board, and the length of the line between the PCB patterns can be shortened to improve the electrical performance. .

Claims (3)

칩(1)상의 칩 패드(2)와 다층 유연성 회로 보드(multilayer flexible circuit board ; 3)의 보드패드(4)를 접착수단(6)을 이용하여 연결하는 단계 ; 상기 과정으로 형성된 각 보드패드(4)의 메탈라인(7)이 보드의 한 방향으로 배열된 형태로 리드(8)를 배열하는 단계 ; 접착제(9)를 사용하여 칩(1)의 접착된 보드들을 성로 접착하는 단계 ; 칩(1)과 다층유연성회로보드(3)를 폴리싱(polishing)하여 리드(8)를 노출시키는 단계 ; 노출된 리드(8)를 접착수단(6)을 이용하여 기판(10)에 연결시키는 단계로 이루어지는 것을 특징으로 하는 반도체 패키지 제조방법.Connecting the chip pad 2 on the chip 1 and the board pad 4 of the multilayer flexible circuit board 3 using the bonding means 6; Arranging the leads 8 in such a manner that the metal lines 7 of the board pads 4 formed in the above process are arranged in one direction of the board; Adhesively bonding the bonded boards of the chip 1 with the adhesive 9; Polishing the chip 1 and the multilayer flexible circuit board 3 to expose the leads 8; Connecting the exposed lead (8) to the substrate (10) using an adhesive means (6). 제1항에 있어서, 상기 보드패드(4)는 Au,Ag등의 전도성 물질로 도금시키는 것을 특징으로 하는 반도체 패키지 제조방법.The method of claim 1, wherein the board pad is plated with a conductive material such as Au or Ag. 제1항에 있어서, 상기 칩(1)과 보드패드(4) 및 리드(8)가 노출된 칩과 기판(10)을 접착시키기 위한 접착수단(6)으로 이방성 도전페이스트나 필름을 사용하는 것을 특징으로 하는 반도체 패키지 제조방법.The method of claim 1, wherein an anisotropic conductive paste or film is used as an adhesive means 6 for bonding the chip 1, the board pad 4, and the chip 8 exposed to the chip 8 and the substrate 10. A semiconductor package manufacturing method characterized in that.
KR1019910025347A 1991-12-30 1991-12-30 Method for manufacturing of semiconductor package KR950005493B1 (en)

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KR1019910025347A KR950005493B1 (en) 1991-12-30 1991-12-30 Method for manufacturing of semiconductor package

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KR1019910025347A KR950005493B1 (en) 1991-12-30 1991-12-30 Method for manufacturing of semiconductor package

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KR930015147A KR930015147A (en) 1993-07-23
KR950005493B1 true KR950005493B1 (en) 1995-05-24

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