KR950004944A - Monitor subtitle shake protection circuit - Google Patents

Monitor subtitle shake protection circuit Download PDF

Info

Publication number
KR950004944A
KR950004944A KR1019930012997A KR930012997A KR950004944A KR 950004944 A KR950004944 A KR 950004944A KR 1019930012997 A KR1019930012997 A KR 1019930012997A KR 930012997 A KR930012997 A KR 930012997A KR 950004944 A KR950004944 A KR 950004944A
Authority
KR
South Korea
Prior art keywords
output
signal
horizontal
synchronization signal
subtitle
Prior art date
Application number
KR1019930012997A
Other languages
Korean (ko)
Other versions
KR960004815B1 (en
Inventor
한석진
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019930012997A priority Critical patent/KR960004815B1/en
Publication of KR950004944A publication Critical patent/KR950004944A/en
Application granted granted Critical
Publication of KR960004815B1 publication Critical patent/KR960004815B1/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • H04N5/21Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Studio Circuits (AREA)
  • Synchronizing For Television (AREA)

Abstract

본 발명은 모니터의 자막 떨림 방지 회로에 관한 것으로, 종래에는 수평, 수직 동기신호에 따라 자막 표시 위치를 결정하여 티브이 화면에 자막을 표시함으로 동기 신호의 구간에 잡음이 혼입되면 자막이 상하좌우로 떨리는 현상이 발생되는 문제점이 있었다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a subtitle anti-shake circuit of a monitor. Conventionally, a subtitle is shaken up, down, left, and right when noise is mixed in a section of a sync signal by determining a caption display position according to a horizontal and vertical sync signal and displaying a caption on a TV screen. There was a problem that the phenomenon occurs.

이러한 점을 감안하여 본 발명에서는 수평 동기 신호의 구간을 계수함에 따라 설정 기준값과 비교하고 비교값이 일치하면 수평동기 신호를 인에이블시키며 이 수평동기신호로 수직 동기 신호의 구간을 계수하여 설정 기준값과 비교하고 비교값이 일치하면 수직동기신호를 인에이블시킨다. 따라서, 일정시간마다 동기신호를 인에이블시킴으로 잡음을 제거하여 정확한 동기신호가 발생됨으로 자막의 떨림을 방지할 수 있다.In view of the above, the present invention compares the set reference value with counting the interval of the horizontal synchronization signal, and enables the horizontal synchronization signal if the comparison value is matched. If the comparisons match, the vertical synchronization signal is enabled. Therefore, by activating the synchronization signal every predetermined time, noise is removed to generate an accurate synchronization signal, thereby preventing subtitles from shaking.

Description

모니터의 자막 떨림 방지 회로Monitor subtitle shake protection circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 종래 모니터의 자막 출력 회로 블럭도. 제 2 도는 제 1 도에 있어서, 동기 신호의 파형도. 제 3 도는 종래 자막 떨림시 동기신호 파형의 예시도, 제 4 도는 본 발명 모니터의 자막 떨림 방지 회로 블럭도. 제 5 도는 제 4 도에 있어서, 동기 정형부의 회로도, 제 6 도에 있어서, 각부의 파형도.1 is a block diagram of a subtitle output circuit of a conventional monitor. 2 is a waveform diagram of a synchronization signal according to FIG. 1; 3 is an exemplary diagram of a conventional subtitle shake signal waveform, and FIG. 4 is a block diagram of a subtitle shake prevention circuit of the present invention. FIG. 5 is a circuit diagram of a synchronous shaping section in FIG. 4, and a waveform diagram of each section in FIG.

Claims (2)

수평, 수직 동기신호(Hsync)(Vsync)의 구간을 계수함에 따라 설정 기준값과 비교하고 비교값이 일치하면 정형된 수평, 수직 동기신호(Hs)(Vs)를 출력하는 동기정형부(3)와, 이 동기정형부(3)의 출력(Hs)(Vs)에 따라 트브이 화면의 자막 표시 위치를 결정하는 동기부(1)와, 이 동기부(1)의 출력(V1)에 따라 자막신호(V0)를 출력하는 자막 출력부(2)로 구성함을 특징으로 하는 모니터의 자막 떨림 방지 회로.A synchronous shaping unit 3 which compares the set reference value by counting the intervals of the horizontal and vertical synchronization signals Hsync (Vsync) and outputs the shaped horizontal and vertical synchronization signals Hs (Vs) when the comparison values match. A synchronization unit 1 for determining the caption display position of the TV screen according to the output Hs (Vs) of the synchronization correction unit 3, and a subtitle according to the output V 1 of the synchronization unit 1; A caption shake prevention circuit of a monitor, characterized by comprising a caption output section (2) for outputting a signal (V 0 ). 제 1 항에 있어서, 동기 정형부(3)는 수평동기신호(Hsync)에 리세트되어 클럭(CLK)을 계수하는 카운터(4)와, 이 카운터(4)의 출력(V4)을 설정기준값(Vref1)과 비교하는 비교기(5)와, 상기 수평동기신호(Hsync)를 일측입력단에 입력받음과 아울러 클럭(CLK)을 입력받아 상기 비교기(5)의 출력(V4)에 따라 래치신호(V6)를 출력하는 플립플롭(6)과, 상기 수평동기신호(Hsync)와 상기 플립플롭(6)의 출력(V6)을 논리합하여 정형된 수평동기신호(Hs)를 출력하는 오아게이트(OR1)와, 수직동기신호(Vsync)에 리세트되어 상기 오아게이트(OR1)의 출력(Hs)를 계수하는 카운터(7)와, 이 카운터(7)의 출력(V7)과 설정기준값(Vref2)을 비교하는 비교기(8)와, 상기 수직동기신호(Vsync)를 일측입력단(J)에 입력받음과 아울러 클럭(CLK)을 입력받아 상기 비교기(8)의 출력(V8)에 따라 래치신호(V9)를 출력하는 플립플롭(9)과, 상기 수직동기신호(Vsync)와 상기 플립플롭(9)의 출력(V9)을 논리합하여 정형된 수직동기신호(Vs)를 출력하는 오아게이트(OR2)로 구성함을 특징으로 하는 모니터의 자막 떨림 방지 회로.The method of claim 1, wherein the synchronization shaping unit 3 is set the output (V 4) of the counter 4, a counter 4, which is reset in the horizontal synchronizing signal (Hsync) count the clock (CLK) reference value A comparator 5 comparing with (Vref 1 ) and the horizontal synchronous signal (Hsync) are input to one input terminal, and a clock (CLK) is input to the latch signal according to the output (V 4 ) of the comparator (5). Iowa outputting a flip-flop 6 and the horizontal synchronization signal (Hsync) and an output (V 6) the horizontal synchronizing signal (Hs) shaping the logical sum of the flip-flop 6 which outputs (V 6) the gate (OR 1 ), a counter 7 reset to the vertical synchronization signal Vsync to count the output Hs of the oragate OR 1 , and an output V 7 of the counter 7 and a setting. A comparator 8 for comparing a reference value Vref 2 and the vertical synchronization signal Vsync are inputted to one side input terminal J, and a clock CLK is received to output V 8 of the comparator 8 . According to the latch signal (V A flip-flop 9 for outputting 9) and an OR gate for outputting a shaped vertical synchronous signal Vs by ORing the vertical synchronization signal Vsync and the output V 9 of the flip-flop 9. 2 ) a subtitle shake prevention circuit of a monitor, characterized by consisting of: ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930012997A 1993-07-10 1993-07-10 Osd character anti-shaking circuit of monitor KR960004815B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930012997A KR960004815B1 (en) 1993-07-10 1993-07-10 Osd character anti-shaking circuit of monitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930012997A KR960004815B1 (en) 1993-07-10 1993-07-10 Osd character anti-shaking circuit of monitor

Publications (2)

Publication Number Publication Date
KR950004944A true KR950004944A (en) 1995-02-18
KR960004815B1 KR960004815B1 (en) 1996-04-13

Family

ID=19359083

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930012997A KR960004815B1 (en) 1993-07-10 1993-07-10 Osd character anti-shaking circuit of monitor

Country Status (1)

Country Link
KR (1) KR960004815B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000039881A (en) * 1998-12-16 2000-07-05 서평원 World standard time signal information service method using voice recognition

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000039881A (en) * 1998-12-16 2000-07-05 서평원 World standard time signal information service method using voice recognition

Also Published As

Publication number Publication date
KR960004815B1 (en) 1996-04-13

Similar Documents

Publication Publication Date Title
KR100243799B1 (en) Odd/even field detector for video signals
GB2263028A (en) Detecting odd and even fields of a video signal
KR950004944A (en) Monitor subtitle shake protection circuit
US5133008A (en) Image signal processing device
KR20010030681A (en) Video signal character converting device and method of the same
KR940008492B1 (en) Error action preventing circuit of character producing circuit
JPS61172484A (en) Video field decoder
US6433829B1 (en) Signal processing apparatus for setting up vertical blanking signal of television set
KR200141097Y1 (en) A circuit for preventing word-waving
KR0166860B1 (en) Specific line detecting apparatus of composite image signal
JP2001285669A (en) Synchronizing signal processing circuit and display device
KR19980703637A (en) Vertical synchronization signal detector
KR100239980B1 (en) Horizontal line counter stabilization in a video receiver
KR0176543B1 (en) Sync. signals generating apparatus
US7705917B2 (en) Method and circuit for extracting synchronization signals in a video signal
KR950005765Y1 (en) Apparatus for generating vertical sync signal for digital tv
KR950703253A (en) TV LINE AND FIELD DETECTION APPARATUS WITH GOOD NOISE IMMUNITY
US5357545A (en) Synchronizing signal detecting circuit
KR970031313A (en) Synchronization detection circuit
JP2743041B2 (en) Image display device
KR960000831Y1 (en) Anti-trembling circuit of osd apparatus
JP2811067B2 (en) Tuning display circuit
KR100233712B1 (en) A circuit for compensating horizontal period delay signal
KR900007907B1 (en) Synchronizing protecting circuit for video system
JPS62150977A (en) Circuit for erasing step-out picture

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080319

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee