KR950004839B1 - Metal wiring method of semiconductor device - Google Patents
Metal wiring method of semiconductor device Download PDFInfo
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- KR950004839B1 KR950004839B1 KR1019920008259A KR920008259A KR950004839B1 KR 950004839 B1 KR950004839 B1 KR 950004839B1 KR 1019920008259 A KR1019920008259 A KR 1019920008259A KR 920008259 A KR920008259 A KR 920008259A KR 950004839 B1 KR950004839 B1 KR 950004839B1
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- oxide film
- plating process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
Description
제1도 내지 제2도는 종래의 금속 배선방법을 나타낸 예시도.1 to 2 are exemplary views showing a conventional metal wiring method.
제3도는 본 발명에 따른 금속 배선방법의 공정도.3 is a process diagram of a metal wiring method according to the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : 실리콘 기판 2 : 산화막1: silicon substrate 2: oxide film
3 : 촉매체 4 : 포토레지스터3: catalyst body 4: photoresist
5 : 플러그 6 : 알루미늄 배선5: plug 6: aluminum wiring
7 : 메탈 필름7: metal film
본 발명은 반도체의 금속 배선방법에 관한 것으로서, 특히 무전해 도금방식을 채택하고, 금속 에치공정을 하지 않음에 따라 스텝 커버리지(Step Coverage) 개선에 적당하도록 한 반도체의 금속 배선방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal wiring method of a semiconductor, and more particularly, to a metal wiring method of a semiconductor that is adapted to improve step coverage by adopting an electroless plating method and not performing a metal etch process.
종래 반도체의 금속 배선방법은 제1도에 도시된 바와 같이 실리콘 기판(1)에 산화막(2)을 데포지션하고, 금속 배선과 접속될 부위에 콘택홀을 만든 다음 콘택홀 내부에 팔라듐(Pd) 또는 몰리브덴(Mo)등을 데포지션하여((a(도) 콘택홀 내에 실리콘 기판(1)을 화확 반응시켜 실리사이드(Silicide)화 되게 하여 촉매체가 되게 함으로써 무전해 도금을 하여 금속 플러그를 형성 ((b)도)시키게 된다.In the conventional metal wiring method, as shown in FIG. 1, the oxide film 2 is deposited on the silicon substrate 1, a contact hole is formed in a portion to be connected to the metal wiring, and then palladium (Pd) is formed inside the contact hole. Alternatively, by depositing molybdenum (Mo) or the like ((a), the silicon substrate 1 is chemically reacted in the contact hole to be silicided to become a catalyst, thereby forming a metal plug by electroless plating (( b).
또한, 제2도는 다수층으로 설치된 금속 배선의 연결을 위해 비아홀(VIA Hall)을 형성한 것으로서, 하나의 금속 배선층(예 : 알루미늄)(6)상에 산화막(2)을 데포지션한 후 소정의 부분에 비아홀이 형성((a)도)되도록 하며 알루미늄 배선(6)은 자기 촉매제 가능을 하게 되어 무전해 도금시 자연적으로 금속 플러그(5)가 형성((b)도)된다.In addition, FIG. 2 shows a via hole for connecting metal wires installed in a plurality of layers, and deposits an oxide film 2 on one metal wire layer (for example, aluminum). The via hole is formed in the portion ((a) also) and the aluminum wiring 6 becomes self-catalytically possible, so that the metal plug 5 is naturally formed ((b) in electroless plating).
무전해 도금기술에 관하여 미국 특허 제4259,409(1981.5.31공개)에 잘 기술되어 있다.The electroless plating technique is well described in US Pat. No. 4,259,409 (published May 5, 1981).
이러한 종래 반도체의 금속 배선방법은 반도체 소자의 직접도가 높아짐에 따라 콘택홀의 형상비(Aspect Ratio)가 커지게 되어 베리어 메탈을 스퍼터링 방법에 의해 증착할 경우 스탭 커버리지가 악화되어 콘택 및 비아홀의 바닥부분이 침식되므로 접합 누설(Junction Leakage)이 증가하거나 접합이 불량하게 되고, 접착도가 약화되어 소자의 신뢰도 및 특성이 저하되는 문제점이 발생하게 된다.In the conventional metal wiring method of the semiconductor, as the directivity of the semiconductor device increases, the aspect ratio of the contact hole increases, and when the barrier metal is deposited by the sputtering method, the step coverage becomes worse and the bottom portions of the contacts and the via holes are deteriorated. As a result of erosion, a junction leakage is increased or a junction is deteriorated, and thus adhesion is weakened, thereby deteriorating reliability and characteristics of the device.
본 발명은 상기와 같은 문제점을 해결하기 위해 금속 에치 공정을 배제하고 문전해 도금방법을 이용하여 스텝 커버리지를 개선시킬 수 있도록 한 것으로서, 본 발명의 목적은 반도체의 금속 배선방법에 있어서, 실리콘 기판 위에 산화막고 포토레지스트를 차례로 데포지션한 후, 콘택홀을 형성하고, 표면 활성화를 위한 배선부 표면 처리 공정과, 상기 공정 후 무전해 도금액에 담구어 촉매용 메탈 필름을 형성시키는 제1차 도금공정과, 상기 제1차 도금 공정 완료 후 포토레지스터를 제거하고 무전해 도금액에 다시 담구어 자기 촉매 반응에 의해 소정 두께의 필름으로 성장시키는 제2차 도금공정으로 이루어지는 반도체의 금속 배선방법을 제공하는데 있다.The present invention is to eliminate the metal etch process in order to solve the above problems and to improve the step coverage by using an electrolytic plating method, an object of the present invention is to provide a method for forming a semiconductor substrate on a silicon substrate. After depositing the oxide film and the photoresist in order, forming a contact hole, and performing a surface treatment step of the wiring part for surface activation, and a first plating step of immersing it in an electroless plating solution to form a catalyst metal film after the step; After the completion of the first plating process, the photoresist is removed, and the second metal plating process is performed by a second plating process of immersing again in an electroless plating solution to grow into a film having a predetermined thickness by a self-catalytic reaction.
이하 첨부된 도면에 의해 상세히 설명하면 다음과 같다.Hereinafter, described in detail by the accompanying drawings as follows.
제3도는 본 발명에 따른 반도체의 금속 배선방법을 도시한 것으로서, 먼저 실리콘 기판(1) 위에 산화막과 포토레지스터를 데포지션한 후, 금속 배선을 하기 위한 소정위치의 절연산화막(2)에 콘택홀을 형성한 후 배선부 표면 처리공정을 한다. 즉, 실리콘 기판(1)에 절연산화막(2) 및 포토레지스터(4)가 데포지션되고, 금속 배선위치의 콘택홀이 형성되어 있는 상태에서 불화수소(HF)에 담구어 콘택 리플로우(Contact Reflow)시 형성된 열산화막을 제거하고 표면을 활성화시킨 후 PdCl2용액을 도포하여 실리콘 기판(1)과 산화막(2) 표면을 활성화시킨후 탈이온수(D.I.Water)로 세척한다.3 illustrates a metal wiring method of a semiconductor according to the present invention. First, an oxide film and a photoresist are deposited on a silicon substrate 1, and then a contact hole is formed in an insulating oxide film 2 at a predetermined position for metal wiring. After the formation of the wiring portion surface treatment process. In other words, contact reflow is immersed in hydrogen fluoride (HF) in a state in which the insulating oxide film 2 and the photoresist 4 are deposited on the silicon substrate 1 and a contact hole at a metal wiring position is formed. After removing the thermal oxide film formed on the substrate and activating the surface, PdCl 2 solution is applied to activate the surface of the silicon substrate 1 and the oxide film 2 and then washed with DI water.
상기 공정 후 (b)도에 도시된 바와 같이 무전해 도금액(Ni-B)에 담구어 제1차 도금 공정을 행하면 화확 반응에 의해 실리콘 기판(1)과 산화막(2) 및 포토레지스터(4)의 표면에 촉매제인 메탈 필름(7)이 형성되며, 이때 메탈 필름(7)은 촉매 역할을 할 정도로 충분히 얇게 수백 Å정도 형성시킨다.After the above process, as shown in (b), the first plating process is performed by dipping in an electroless plating solution (Ni-B). Thus, the silicon substrate 1, the oxide film 2, and the photoresist 4 are formed by chemical reaction. The metal film 7 which is a catalyst is formed on the surface of the metal film 7, and the metal film 7 is formed to be thin enough to serve as a catalyst for several hundreds of microns.
이때, 메탈필름(7)의 성장은 등방성을 지니므로 스퍼터링시 문제가 되는 스텝 커버리지 문제를 해결하게 되며, 제1차 도금공정은 100℃ 이하의 수용액(NiSo4+DMAB)(NiSo4+Na2WO4+DMAB)에서 실시한다. 여기서, DMAB는 De Methyle Amine Borone으로서 환원제이다.At this time, since the growth of the metal film 7 is isotropic, the step coverage problem, which is a problem in sputtering, is solved, and the first plating process is an aqueous solution (NiSo 4 + DMAB) (NiSo 4 + Na 2 ) of 100 ° C. or less. WO 4 + DMAB). DMAB is a reducing agent as De Methyle Amine Borone.
그 다음, 포토레지스터(4)를 스트립하면 (c)도에서와 같이 배선을 위한 콘택홀 주위에만 메탈필름(7)이 남게 되며, 그 이후에 다시 무전해 도금액에 담구어 제2차 도금 공정을 행하면 메탈필름(7)이 자기 촉매제로 작용하게 되고, 또한 자기 촉매 반응에 의해 성장하여 (d)도에서와 같이 원하는 두께의 금속 배선 플러그(5)가 형성된다. 이 때, 금속 배선 플러그(5)의 데포지션 비율 및 조성은 각 수용액(NiSo4, DMAB, Na2W04)의 농도를 조절함에 따라 가능하게 된다.Then, when the photoresist 4 is stripped, as shown in (c), the metal film 7 remains only around the contact hole for wiring, and afterwards, the second plating process is performed by immersing it again in the electroless plating solution. In this case, the metal film 7 acts as a self-catalyst, and grows by the self-catalytic reaction to form a metal wiring plug 5 having a desired thickness as shown in (d). At this time, the deposition rate and composition of the metal wiring plug 5 can be adjusted by adjusting the concentration of each aqueous solution (NiSo 4 , DMAB, Na 2 W0 4 ).
이상에서 상술한 바와 같이 본 발명은 실리콘 기판 위의 산화막을 열고 금속 배선 콘택홀을 형성하는 공정과, 상기 콘택홀 형성 후 금속 배선 위치를 제외한 모든 부분을 포토레지스터로 도포한 후 표면 활성화를 위한 배선부 표면 처리 공정과, 상기 공정 후 무전해 도금액에 담구어 수백 Å의 메탈 필름을 형성시키는 제1차 도금공정고, 상기 공정 완료후 포토레지스터를 스트립하고 무전해 도금액에 다시 담구어 자기 촉매반응에 의해 소정 두께의 필름으로 성장시키는 제2차 도금공정으로 이루어져, 포토레지스터 제거 후 금속 배선을 형성하게 되어 반사율에 의한 노칭(Notcbing)을 방지하고 메탈 필름의 열 팽창계수가 낮기 때문에 스트레스로 인하여 발생되는 크래킹(Stress Cracking)이 방지될 뿐만 아니라 메탈 필름이 고융점 금속이므로 이후 공정 처리에 유리하며, 메탈 필름이 등방성으로 성장되어 스탭 커버리지가 개선됨으로써 반도체 소자의 신뢰성 향상에 기여할 수 있는 것이다.As described above, the present invention provides a process for forming a metal wiring contact hole by opening an oxide film on a silicon substrate, and after forming the contact hole, coating all portions except the metal wiring position with a photoresist and then wiring for surface activation. The secondary surface treatment process, and the first plating process to immerse the electroless plating solution to form hundreds of 메탈 metal film after the step, and after the completion of the process, the photoresist is stripped and immersed again in the electroless plating solution for autocatalytic reaction. By the second plating process to grow into a film having a predetermined thickness, and the metal wiring is formed after the photoresist is removed to prevent notching due to the reflectance and is generated due to stress because the thermal expansion coefficient of the metal film is low. Stress cracking is not only prevented, but the metal film is a high melting point metal, which is subsequently processed. Glass, and a metal film is grown isotropically improving staff coverage whereby it can contribute to improve the reliability of the semiconductor device.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920008259A KR950004839B1 (en) | 1992-05-15 | 1992-05-15 | Metal wiring method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019920008259A KR950004839B1 (en) | 1992-05-15 | 1992-05-15 | Metal wiring method of semiconductor device |
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| KR930024097A KR930024097A (en) | 1993-12-21 |
| KR950004839B1 true KR950004839B1 (en) | 1995-05-13 |
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| KR100334959B1 (en) * | 1998-10-29 | 2002-06-20 | 박종섭 | Metal wiring method of semiconductor device _ |
| KR100454633B1 (en) * | 2002-01-04 | 2004-11-05 | 재단법인서울대학교산학협력재단 | Treatment method of wafer surface |
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