KR950002953B1 - Manufacturing method of semiconductor device using multi-layer metal wiring structure - Google Patents
Manufacturing method of semiconductor device using multi-layer metal wiring structure Download PDFInfo
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- KR950002953B1 KR950002953B1 KR1019920009979A KR920009979A KR950002953B1 KR 950002953 B1 KR950002953 B1 KR 950002953B1 KR 1019920009979 A KR1019920009979 A KR 1019920009979A KR 920009979 A KR920009979 A KR 920009979A KR 950002953 B1 KR950002953 B1 KR 950002953B1
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 62
- 239000002184 metal Substances 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000000034 method Methods 0.000 claims abstract description 58
- 238000005530 etching Methods 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 238000000206 photolithography Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 55
- 239000011229 interlayer Substances 0.000 claims description 18
- 238000005229 chemical vapour deposition Methods 0.000 claims description 14
- 229910052782 aluminium Inorganic materials 0.000 claims description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 13
- 238000001020 plasma etching Methods 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims 1
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000000992 sputter etching Methods 0.000 abstract description 2
- 238000007796 conventional method Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1도는 종래의 제조방법을 설명하기 위한 평탄화용 포토 레지스트를 이용한 에치백으로 식각한 상태를 보인 반도체 장치의 구조.1 is a structure of a semiconductor device showing a state of etching with an etch back using a planarization photoresist for explaining a conventional manufacturing method.
제2도 (a)∼(h)는 본 발명에 의한 제조방법을 보여주는 반도체 장치의 단면도.2A to 2H are cross-sectional views of a semiconductor device showing a manufacturing method according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 11 : 실리콘기판 2, 12, 17 : 제1차 금속층1, 11: silicon substrate 2, 12, 17: primary metal layer
3, 13 : 식각중단층 4, 14, 16 : 연결금속층(필라)3, 13 etching etch stop layer 4, 14, 16: connection metal layer (pillar)
5, 18, 18A : 층간 절연막 15, 15A, 19, 20 : 감광막5, 18, 18A: interlayer insulating film 15, 15A, 19, 20: photosensitive film
21 : 제2차 금속층21: secondary metal layer
본 발명은 다층금속 배선구조를 갖는 반도체 장치의 제조방법에 관한 것으로서, 더욱 구체적으로는 적어도 2층의 금속 배선구조에서 금속배선간 알루미늄 필라접촉의 성능을 개선시킨 반도체 장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a multi-layered metal wiring structure, and more particularly, to a method of manufacturing a semiconductor device having improved performance of aluminum pillar contact between metal wirings in at least two layers of metal wiring structures.
다층구조의 반도체 장치를 제조하는 종래의 방법을 제1도에 의거하여 설명하면 다음과 같다.A conventional method of manufacturing a semiconductor device having a multilayer structure will be described with reference to FIG. 1 as follows.
제1도는 종래의 제조방법을 설명하기 위해 평탄화용 포토 레지스트를 에치백방법으로 식각한 공정을 보여주기 위한 반도체 장치의 단면도이다.1 is a cross-sectional view of a semiconductor device for illustrating a process of etching a flattening photoresist by an etch back method to explain a conventional manufacturing method.
제1도에서, 실리콘기판(1)상에 소정패턴으로 제1차 금속층(2)이 형성되어 있고, 상기 상면에 소정패턴으로 식각중단층(3)을 형성하고, 이 식각중단층 전면에 다층금속간 전기적 접촉을 위해 필라(Pillar : 4)가 형성되며, 그리고 상기 층간 절연막(5)을 화학 기상증착(Chemical Vapor Deposition) 방법으로 형성하는 과정을 나타낸 것이다.In FIG. 1, a primary metal layer 2 is formed on a silicon substrate 1 in a predetermined pattern, and an etch stop layer 3 is formed on the upper surface in a predetermined pattern. Pillar (4) is formed for the electrical contact between the metal, and shows the process of forming the interlayer insulating film (5) by the chemical vapor deposition (Chemical Vapor Deposition) method.
이러한 상태에서, 종래의 방법은 2차 금속층을 화학증착(CVD : Chemical Vapor Deposition) 방법을 이용하지 않고 물리적 기상증착(PVD : Physical Vapor Deposition) 방법을 사용함으로써 2차 금속층의 스텝 커버리지가 가장 심각한 문제점으로 대두되고 있으나 이것은, 알루미늄 필라(Aluminum Pillar)를 이용함으로써 해결할 수 있다.In this state, the conventional method uses the physical vapor deposition (PVD) method instead of the chemical vapor deposition (CVD) method of the secondary metal layer, so that the step coverage of the secondary metal layer is the most serious problem. Although it is emerging as, it can be solved by using an aluminum pillar (Aluminum Pillar).
그러나, 알루미늄 필라를 이용하는 공정상에서 문제가 존재하게 된다.However, a problem exists in the process using aluminum pillars.
그것은 1차 금속위에 알루미늄 필라를 형성한 다음 층간 절연막을 증착할 때에 화학적 증착(CVD) 방법을 이용하게 되는데 이 화학적 증착(CVP) 방법은 스텝 커버리지 특성이 우수하기 때문에 1차 금속과 필라에 의하여 형성된 표면의 굴곡이 줄어들지 않음으로써 2차 금속층을 증착하기 전에 평탄화에 어렵다.It uses a chemical vapor deposition (CVD) method to form an aluminum pillar on the primary metal and then deposit an interlayer insulating film. The chemical vapor deposition (CVP) method is formed by the primary metal and the pillar because of its excellent step coverage characteristics. The curvature of the surface is not reduced, making it difficult to planarize before depositing the secondary metal layer.
따라서, 평탄화를 성공적으로 수행함으로써 특성이 좋은 알루미늄 필라를 형성할 수 있다.Thus, by successfully performing planarization, it is possible to form an aluminum pillar having good properties.
종래의 방법에서 가장 일반적으로 수행되었던 평탄화의 방법으로는 포토레지스트와 반응성 이온식각을 이용한 에치백 기술을 주로 이용하였다.As the planarization method which has been most commonly performed in the conventional method, an etch back technique using photoresist and reactive ion etching is mainly used.
상기 방법의 몇가지 단점을 나열하면 첫째, 장비 의존성이 심하고 둘째, 패턴의 조밀도에 대한 의존성이 심하며 셋째, 패턴의 굴곡에 대한 의존성이 심하기 때문에 공정시 각별한 주의가 요구된다.Some of the shortcomings of the above method are listed. First, since equipment dependence is severe, and second, pattern dependence is severely dependent. Third, pattern dependence is severely demanded.
장비의 의존성이란 포토레지스트의 도포 및 도포공정을 포함하여 반응성 이온식각 장비의 식각 균일도, 층간 절연막의 두께변화 및 포토레지스트와 층간절연층의 식각선택비등 필라를 사용하는 방법에서는 층간 절연막의 두께가 종래의 것보다 일반적으로 크기 때문에 상기의 과정의 어느 한 부분의 조건을 만족하지 못하면 기대하는 결과를 얻을 수 없다.The dependence of equipment means that the thickness of the interlayer insulating film is conventional in the method of using a pillar such as the etching uniformity of the reactive ion etching equipment, the thickness change of the interlayer insulating film, and the etching selectivity of the photoresist and the interlayer insulating layer, including the application and application process of the photoresist. Since it is generally larger than, the expected results are not obtained if the conditions of any part of the above process are not satisfied.
특히, 식각선택비 및 식각 균일도는 장비 의존성이 많으며 패턴의 조밀도 및 패턴의 굴곡에 대한 평탄화 정도가 달라지게 되며, 포토레지스트를 에치백 하기전에 층간 절연막을 증착하는 과정에서 인사이튜 프라나리제이션(Insitu Planarization)을 수행한 다음 포토레지스트 에칭백을 수행하나 패턴의 조밀도와 굴곡의 크기에 따라 많은 제한적 요소를 가지므로 근본적인 해결책은 아니며 선택에 있어 주의를 해야한다.In particular, the etching selectivity and the uniformity of the etching are highly dependent on the equipment, and the density of the pattern and the degree of planarization of the pattern are changed. After performing insitu planarization, the photoresist etch back has many limitations depending on the density of the pattern and the size of the curve, so it is not a fundamental solution and care must be taken in choosing.
또한, 포토레지스트 에치백 방법을 사용함에 있어 가장 심각한 문제는 평탄화가 되는 범위가 수십 마이크로 정도로 국부적(local area)이다.In addition, the most serious problem in using the photoresist etch back method is a local area in which the planarization range is several tens of microns.
따라서, 본 발명의 기계 및 화학적 평탄화 방법을 이용하여 평탄화 범위를 넓힘으로서 스텝 커버리지가 줄어들어 전기적 신뢰성을 향상시키는 다층금속 배선구조를 이용한 반도체 장치의 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device using a multi-layered metal interconnection structure which reduces step coverage by improving the planarization range by using the mechanical and chemical planarization methods of the present invention to improve electrical reliability.
상기 목적을 달성하기 위하여 본 발명의 일특징에 의하면, 실리콘기판(11)상에 제1차 금속층(12)과 식각중단층(13)을 증착하고, 그 상면에 연결금속층(14)을 차례로 증착하고, 그위에 소정의 패턴 감광막(15)를 도포한 다음 포토리소그라피 및 반응성 이온식각 방법을 이용하여 소정의 패턴 필라(16)을 형성하는 공정과, 상기 필라(16)상에 포토리소그라피 및 반응성 이온식각 방법으로 제1차 금속층(17)을 형성하는 공정과, 이어 상기 전면에 제1차 금속과 제2차 금속층의 층간 절연막(18)을 화학증착(CVD)방법으로 증착하는 공정과 상기 층간 절연막(18)을 기계적 화학적 평탄화를 마치고 필라 위에 남아있는 층간 절연막(18A)을 포토레지스트 에치백 처리하는 공정과, 이어 상기 평탄화한 다음 제2차 금속층(21)을 증착한 후 감광막(20)을 소정의 패턴으로 형성한 다음 반응성 이온 식각방법으로 식각 제거하여 제2차 금속층을 형성하는 공정을 포함한다.In order to achieve the above object, according to one feature of the present invention, the primary metal layer 12 and the etch stop layer 13 are deposited on the silicon substrate 11, and the connection metal layer 14 is sequentially deposited on the upper surface thereof. And applying a predetermined pattern photosensitive film 15 thereon to form a predetermined pattern pillar 16 using photolithography and reactive ion etching methods, and photolithography and reactive ions on the pillar 16. Forming a first metal layer 17 by an etching method, and then depositing an interlayer insulating film 18 of a first metal and a second metal layer on the entire surface by a chemical vapor deposition (CVD) method and the interlayer insulating film (18) the photoresist etch-back process of the interlayer insulating film (18A) remaining on the pillar after the mechanical chemical planarization, and then the planarizing and then depositing the second metal layer (21) after the photoresist film 20 Formed into a pattern of Etching to remove the eungseong ion etching method includes a step of forming a second metal layer.
이하 본 발명의 실시예를 설명한다.Hereinafter, embodiments of the present invention will be described.
제2도는 본 발명의 제조방법을 보여주는 도면으로서, 제2a도는 실리콘기판(11)상에 제1차 금속층(12)의 알루미늄을 소정의 두께로 증착하고, 그위에 식각중단층(13)인 타이타늄-텅스턴을 소정의 두께로 형성한 다음 금속연결층(필라 : Pillar)(14)의 알루미늄을 소정의 두께로 적층하고, 그 상면에 감광막(15)을 형성하는 과정을 나타낸 것이다.FIG. 2 is a view showing a manufacturing method of the present invention. FIG. 2A is a diagram showing the deposition of aluminum of the primary metal layer 12 on a silicon substrate 11 to a predetermined thickness, and the etch stop layer 13 thereon as titanium. After forming a tungsten to a predetermined thickness, the aluminum of the metal connection layer (pillar) 14 is laminated to a predetermined thickness, and the photosensitive film 15 is formed on the upper surface thereof.
제2b도는 감광막(15)을 이용하여 포토리소그라피 및 반응성 이온식각 방법으로 연결금속층(14)을 제거한 다음 필라 패턴(16)을 보여주고 있다.FIG. 2B shows the pillar pattern 16 after the connection metal layer 14 is removed by photolithography and reactive ion etching using the photosensitive film 15.
종래에는 제1차 금속층을 형성한 다음 식각중단층과 중간 연결층을 증착하였으나, 본 발명에서는 제1차 금속층과 식각중단층 및 중간 연결층을 동시에 증착한 후 먼저 중간 연결층인 필라를 형성한 것이다.Conventionally, after forming the primary metal layer, the etch stop layer and the intermediate connection layer are deposited, but in the present invention, the primary metal layer, the etch stop layer, and the intermediate connection layer are deposited at the same time, and then the pillar, which is the intermediate connection layer, is first formed. will be.
상기 방법은 종래의 필라형성법에 비해 개선된 것으로, 포토리소그라피 공정시 금속의 높은 반사율 때문에 생기는 스탠딩 웨이브(Standing wave) 현상에 의한 필라 패턴의 일그러짐을 막아준다.The method is an improvement over the conventional pillar forming method, and prevents the distortion of the pillar pattern due to the standing wave phenomenon caused by the high reflectance of the metal during the photolithography process.
상기 식각중단층은 필라형성 식각시 식각의 마지막 단계에서 식각중단층이 제거된다. 필라형성 식각전에 식각중단층이 제거되게 되면 제1차 금속층이 손상되어 효과를 얻지 못하게 되므로 제1차 금속층의 식각 선택비가 높아야 한다.The etch stop layer is removed from the etch stop layer at the end of the etching during the pillar forming etching. If the etch stop layer is removed before the pillar forming etch, the primary metal layer may be damaged and may not be obtained. Therefore, the etching selectivity of the primary metal layer should be high.
제2c도는 필라(16) 패턴위에 포토리소그라피 및 반응성 이온식각 방법에 이하여 제1차 금속층(17)이 형성된 과정을 나타낸 것이다.FIG. 2C illustrates a process in which the primary metal layer 17 is formed on the pillar 16 pattern following photolithography and reactive ion etching.
제2d도는 제1차 금속층(12)과 제2차 금속층 사이에 층간 절연막(18)으로 실리콘 산화막을 스텝커버리지 특성이 우수한 화학 증착법(CVD)으로 증착하는 과정을 나타낸 것이다.FIG. 2D illustrates a process of depositing a silicon oxide film by chemical vapor deposition (CVD) with excellent step coverage between the primary metal layer 12 and the secondary metal layer with the interlayer insulating film 18.
상기 과정에서 생기는 굴곡을 평탄화하고 연결금속층과 제2차 금속층의 연결을 위하여 연결금속층의 윗부분이 드러나도록 하기 위한 단계이다.This step is to flatten the curvature generated in the process and to expose the upper portion of the connection metal layer for the connection of the connection metal layer and the secondary metal layer.
다층배선 공정에서는 필연적으로 거쳐야 하는 것으로 포토레지스트를 이용한 에칭백 과정이 종래의 기술에서도 일반적으로 사용되고 있다.In the multilayer wiring process, it is inevitably required, and an etching back process using a photoresist is generally used in the related art.
그러나, 종래의 필라형성 공정에서도 포토레지스트를 에치백으로 수행하였다.However, the photoresist was also etched back in the conventional pillar forming process.
상기 과정에서 종래의 방법과 비교하여 새로운 방법으로 실시하였는데, 상기 방법은 기계적 화학적 연마를 통한 평탄화 방법이다.In the process was carried out in a new method compared to the conventional method, the method is a planarization method through mechanical chemical polishing.
본 발명에서는 층간 절연막을 증착한 다음 웨이퍼 표면에 형성되는 굴곡을 기계적 화학적 방법으로 연마처리함으로써 대단히 우수한 평탄화 특성을 얻을 수 있다.In the present invention, very excellent planarization characteristics can be obtained by depositing an interlayer insulating film and then polishing the curvature formed on the wafer surface by a mechanical and chemical method.
종래의 사용하던 포토레지스트 에치백 공정보다 평탄화 범위가 웨이퍼 수준으로 우수하며 평탄화 정도는 웨이퍼를 연마하는 수준을 뛰어난 특성을 얻을 수 있다.The planarization range is superior to the wafer level than the conventional photoresist etchback process, and the degree of planarization is excellent in polishing the wafer.
이때, 주의하여야 할 점은 알루미늄의 강도와 연성이 연결금속층과 다르기 때문에 필라 윗부분의 층간 절연막을 약간은 남겨두어야만 하는데 그 이유는 층간절연물 연마시 필라가 손상을 받지 않도록 하기 위한 것이다.At this time, it should be noted that since the strength and ductility of the aluminum is different from the connecting metal layer, the interlayer insulating film on the upper part of the pillar should be left slightly, so that the pillar is not damaged when the interlayer insulating material is polished.
제2e도는 기계적 화학적 방법으로 평탄화 공정을 마치고 포토레지스트를 도포한 상태를 나타낸 것이다.2e shows a state in which a photoresist is applied after the planarization process is completed by a mechanical and chemical method.
제2f도는 상기 공정을 마치고 위에 남아있는 층간 절연막(18A)을 제거하기 위하여 포토레지스트 에치백 공정을 이용하여 식각하는 과정을 나타낸 것이다.FIG. 2F illustrates a process of etching using a photoresist etch back process to remove the remaining interlayer insulating film 18A after the process.
상기의 공정에서 이미 층간 절연막의 굴곡이 평탄화 되었기 때문에 에치백 공정에 문제가 없으며 필라위에 남아있는 절연막의 두께가 얇으므로 반응성 이온식각 장비의 식각 균일도도 문제가 되지 않는다.Since the curvature of the interlayer insulating film is already flattened in the above process, there is no problem in the etch back process and the thickness of the insulating film remaining on the pillar is thin, so the etching uniformity of the reactive ion etching equipment is not a problem.
제2g도는 평탄화 공정 다음 상기 상면에 알루미늄으로 제2금속층(19)을 소정의 두께로 증착하고 감광막(20)을 형성하는 과정을 나타낸 것이다.2g illustrates a process of depositing a second metal layer 19 with a predetermined thickness of aluminum on the upper surface after the planarization process and forming the photoresist film 20.
제2h도는 상기 감광막(20)을 이용하여 포토리소그라피 공정으로 식각하고, 감광막(20)을 제거하여 패터닝하여 제2차 금속층(21)을 완성된 구조를 보여주고 있다.FIG. 2h illustrates a structure in which the secondary metal layer 21 is completed by etching the photolithography process using the photosensitive film 20 and removing and patterning the photosensitive film 20.
이와 같이, 본 발명에 의해 제조된 다층금속 배선구조는 국부적 평탄화 방법인 포토레지스트 에치백 공정의 단점을 개선하여 웨이퍼 평탄화 방법을 도입함으로써 다층배선의 기술에 많은 발전을 가지게 되며, 알루미늄 필라를 이용함으로 전기적 특성을 개선시키고 소자의 신뢰성을 향상시킬 수 있다.As described above, the multilayer metal interconnection structure manufactured by the present invention improves the disadvantages of the photoresist etchback process, which is a local planarization method, and thus has many developments in the technology of the multilayer interconnection by introducing a wafer planarization method. It can improve the electrical characteristics and improve the reliability of the device.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920009979A KR950002953B1 (en) | 1992-06-09 | 1992-06-09 | Manufacturing method of semiconductor device using multi-layer metal wiring structure |
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| KR1019920009979A KR950002953B1 (en) | 1992-06-09 | 1992-06-09 | Manufacturing method of semiconductor device using multi-layer metal wiring structure |
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| KR950002953B1 true KR950002953B1 (en) | 1995-03-28 |
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