KR950001904A - Gate electrode formation method - Google Patents

Gate electrode formation method Download PDF

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Publication number
KR950001904A
KR950001904A KR1019930011747A KR930011747A KR950001904A KR 950001904 A KR950001904 A KR 950001904A KR 1019930011747 A KR1019930011747 A KR 1019930011747A KR 930011747 A KR930011747 A KR 930011747A KR 950001904 A KR950001904 A KR 950001904A
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KR
South Korea
Prior art keywords
film
tungsten silicide
forming
gate electrode
predetermined thickness
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KR1019930011747A
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Korean (ko)
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KR960008564B1 (en
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나민권
박인환
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김주용
현대전자산업 주식회사
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Priority to KR93011747A priority Critical patent/KR960008564B1/en
Publication of KR950001904A publication Critical patent/KR950001904A/en
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Publication of KR960008564B1 publication Critical patent/KR960008564B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 제조공정중 게이트전극 형성방법에 관한 것으로, 게이트산화막(3) 상부에 불순물이 도핑된 폴리실리콘막(4)을 소정 두께로 형성하는 단계와, 불화수소에 딥하는 단계와, 황산이나 암모늄으로 크리닝하여 오염입자를 제거한 후 순수로 세정하여 건조시키는 단계와, 티타늄막(5)을 소정 두께로 형성하고, 시간지체없이 텅스텐 실리사이드막(6)을 소정 두께로 형성하는 단계와, 상기 텅스텐 실리사이드막(6), 티타늄막(5), 도핑된 폴리실리콘막(4), 게이트산화막(3)을 차례로 식각하여 게이트전극 패턴을 형성한 다음, 열처리하여 상기 도핑된 폴리실리콘막(4)과 텅스텐 실리사이드막(6)의 계면에 강한 TiSi2막(7)을 형성하는 단계를 포함하여 이루어짐으로써, 본 발명은 도핑된 폴리실리콘막과 텅스텐 실리사이드막 사이에 얇은 티타늄막을 증착하여 계면에서 강한 TiSi2결합을 형성하여 텅스텐 실리사이드막의 벗겨짐을 방지할 수 있다.The present invention relates to a method of forming a gate electrode during the manufacturing process of a semiconductor device, comprising the steps of forming a polysilicon film (4) doped with impurities on the gate oxide film (3) to a predetermined thickness, and dip into hydrogen fluoride; Cleaning with pure sulfuric acid or ammonium to remove contaminants, followed by washing with pure water and drying; forming a titanium film 5 to a predetermined thickness; and forming a tungsten silicide film 6 to a predetermined thickness without delay. , The tungsten silicide layer 6, the titanium layer 5, the doped polysilicon layer 4, and the gate oxide layer 3 are sequentially etched to form a gate electrode pattern, and then heat-treated to form the doped polysilicon layer ( 4) and forming a strong TiSi 2 film 7 at the interface of the tungsten silicide film 6, the present invention provides a thin titanium film between the doped polysilicon film and the tungsten silicide film. By depositing a strong TiSi 2 bond at the interface to prevent the tungsten silicide film from peeling off.

또한, 본 발명에서는 프리-실리사이드 크리닝 공정에서도 불화수소 처리후 최종 크리닝 공정시 황산과 암모늄 크리닝 공정으로 종결함으로써 웨이퍼 상태가 친수성이 되도록 하여 오염입자 흡착과 건조시 불량을 방지할 수 있고 불화수소 처리시 흡착된 오염입자를 황산이나 암모늄 크리닝으로 완전히 제거하여 양질의 게이트전극을 형성할 수 있다.In addition, in the present invention, in the pre-silicide cleaning process, the final cleaning process after the hydrogen fluoride treatment is terminated by sulfuric acid and ammonium cleaning process to make the wafer state hydrophilic, thereby preventing contamination during the adsorption of contaminated particles and drying, and during hydrogen fluoride treatment. Adsorbed contaminant particles can be completely removed by sulfuric acid or ammonium cleaning to form a high quality gate electrode.

Description

게이트전극 형성방법Gate electrode formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 게이트전극 형성시 열공정전의 단면도, 제2도는 본 발명에 따라 형성된 게이트전극 단면도.1 is a cross-sectional view before the thermal process when forming the gate electrode according to the present invention, Figure 2 is a cross-sectional view of the gate electrode formed according to the present invention.

Claims (2)

게이트전극 형성방법에 있어서, 게이트산화막(3) 상부에 불순물이 도핑된 폴리실리콘막(4)을 소정 두께로형성하는 단계와, 불화수소애 딥하는 단계와, 황산이나 암모늄으로 크리닝하여 오염입자를 제거한 후 순수로 세정하여 건조시키는 단계와, 티타늄막(5)을 소정 두께로 형성하고, 시간지체 없이 텅스텐 실리사이막(6)을 소정 두께로 형성하는 단계와, 상기 텅스텐 실리사이드막(6), 티타늄막(5), 도핑된 폴리실리콘막(4), 게이트산화막(3)을 차례로 식각하여 게이트전극 패턴을 형성한 다음, 열처리하여 상기 도핑된 폴리실리콘막(4)과 텅스텐 실리사이드막(6)의 계면에 강한 TiSi2막(7)을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 게이트전극 형성방법.In the gate electrode forming method, the polysilicon film (4) doped with impurities on the gate oxide film (3) is formed to a predetermined thickness, the step of dipping into hydrogen fluoride, and cleaning with condensate or ammonium to remove contaminated particles Removing and washing with pure water to dry, forming a titanium film 5 to a predetermined thickness, and forming a tungsten silicide film 6 to a predetermined thickness without time delay, the tungsten silicide film 6, The titanium film 5, the doped polysilicon film 4, and the gate oxide film 3 are sequentially etched to form a gate electrode pattern, and then heat-treated to form the doped polysilicon film 4 and the tungsten silicide film 6 And forming a TiSi 2 film (7) resistant to the interface of the gate electrode. 제1항에 있어서, 열처리 공정시 상기 도핑된 폴리실리콘막(4), 티타늄막(5), 텅스텐 실리사이드막(6)의 증착두께는 각각 1800 내지 2200Å, 270 내지 330Å, 1500 내지 1900Å인 것을 특징으로 하는 게이트전극 형성방법.The deposition thickness of the doped polysilicon film 4, the titanium film 5, and the tungsten silicide film 6 during the heat treatment process is 1800 to 2200 Pa, 270 to 330 Pa, 1500 to 1900 Pa, respectively. A gate electrode forming method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93011747A 1993-06-25 1993-06-25 Gate electrode-forming method KR960008564B1 (en)

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Application Number Priority Date Filing Date Title
KR93011747A KR960008564B1 (en) 1993-06-25 1993-06-25 Gate electrode-forming method

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Application Number Priority Date Filing Date Title
KR93011747A KR960008564B1 (en) 1993-06-25 1993-06-25 Gate electrode-forming method

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KR950001904A true KR950001904A (en) 1995-01-04
KR960008564B1 KR960008564B1 (en) 1996-06-28

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100272653B1 (en) * 1996-12-10 2000-12-01 김영환 Method of manufacturing semiconductor device
KR100367403B1 (en) * 1999-06-28 2003-01-10 주식회사 하이닉스반도체 Method for forming contact of a semiconductor device
KR100436053B1 (en) * 1996-12-24 2004-09-04 주식회사 하이닉스반도체 Method of manufacturing semiconductor device using conductive mask to prevent leakage current
KR100570203B1 (en) * 1998-12-30 2006-08-18 주식회사 하이닉스반도체 Gate electrode formation method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100272653B1 (en) * 1996-12-10 2000-12-01 김영환 Method of manufacturing semiconductor device
KR100436053B1 (en) * 1996-12-24 2004-09-04 주식회사 하이닉스반도체 Method of manufacturing semiconductor device using conductive mask to prevent leakage current
KR100570203B1 (en) * 1998-12-30 2006-08-18 주식회사 하이닉스반도체 Gate electrode formation method
KR100367403B1 (en) * 1999-06-28 2003-01-10 주식회사 하이닉스반도체 Method for forming contact of a semiconductor device

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Publication number Publication date
KR960008564B1 (en) 1996-06-28

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