KR950000145B1 - It ldd structure for ig fet and manufacturing method thereof - Google Patents
It ldd structure for ig fet and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 125000006850 spacer group Chemical group 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 2
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 claims 2
- 239000012535 impurity Substances 0.000 abstract description 3
- 239000007943 implant Substances 0.000 abstract 2
- 230000005684 electric field Effects 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000011038 discontinuous diafiltration by volume reduction Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
제 1 도는 종래기술에 의한 IT LDD 구조의 제조공정을 나타낸 단면도.1 is a cross-sectional view showing a manufacturing process of the IT LDD structure according to the prior art.
제 2 도는 (a) ∼ (e)는 본 발명에 의한 IT LDD 구조의 제조공정을 나타낸 단면도.(A)-(e) is sectional drawing which shows the manufacturing process of IT LDD structure by this invention.
본 발명은 고집적도의 회로에 널리 사용되고 있는 절연 게이트형 전계효과 트랜지스터(Insulated Gate Field Effect Transistor, 이하 IG FET라함)에 관한 것으로, 특히 채널과 소오스·드레인 영역 사이에 저농도영역을 형성시켜 디바이스 내부의 전계강도를 완화시킨 IF LDD(Inverse-T gate Lightly Doped Drain) 구조를 가진 IG FET 장치와 그 제조방법에 관한 것이다.The present invention relates to an Insulated Gate Field Effect Transistor (IG FET), which is widely used in high-integration circuits. In particular, a low concentration region is formed between a channel and a source / drain region. The present invention relates to an IG FET device having an IF-LDD (Inverse-T gate Lightly Doped Drain) structure with moderate field strength and a method of manufacturing the same.
MOS FET(Metal Oxide Sumiconductor FET)로 대표되는 IG FET에 있어서, 디바이스의 고속화와 고집적화를 위해 각 소자의 미세화를 위한 스케일링이 급속히 진전되어 옴에 따라 채널길이가 짧아지고 더욱이 전원전압에 일정하게 유지됨에 따라 디바이스 내부의 전계강도가 증대되어 FET 특성의 불안정 또는 결함의 요인이 되고 있음은 잘 알려진 사실이다.In IG FETs represented by MOS FETs (Metal Oxide Sumiconductor FETs), scaling for the miniaturization of each device is rapidly progressed in order to increase the speed and high integration of the device, as the channel length is shortened and the voltage is kept constant at the supply voltage. It is well known that the electric field strength inside the device is increased, causing instability or defects in the FET characteristics.
즉 스레시홀드 전압, 상호 콘덕턴스, 드레인 접합의 파괴전압 특성 등이 채널영역 또는 그 근처에서 발생되는 펀치스루현상이나 핫 캐리어 효과(Hot carrier effects)에 의해 변동된다. 펀치스루(punch through) 현상은 드레인 공핍층의 확대와 소오스 영역으로의 침투에 의해 소오스-기판 간의 장벽 전위가 감소되면서 발생하여 디바이스의 리크전류의 증대를 가져오기 때문에 소자의 동작에 악영향을 준다. 이러한 펀치스루현상을 방지하기 위하여 채널 하부에 소정의 불순물을 주입하여 주는 것이 유효하게 적용되어 왔으나, 무엇보다도 문제가 되고 있는 것은 핫 캐리어 효과에 의한 제반 문제점인 것이다.That is, the threshold voltage, the mutual conductance, the breakdown voltage characteristics of the drain junction, and the like are changed by the punch-through phenomenon or the hot carrier effects generated in or near the channel region. The punch through phenomenon occurs as the barrier potential between the source and the substrate decreases due to the enlargement of the drain depletion layer and the penetration into the source region, thereby increasing the leakage current of the device, thereby adversely affecting the operation of the device. In order to prevent such a punch-through phenomenon, it has been effectively applied to inject a predetermined impurity in the lower part of the channel, but above all, the problem is caused by the hot carrier effect.
즉, 채널 중의 캐리어가 디바이스의 단축에 따라 드레인 부근에 형성된 고전계에 의해 가속되어 실리콘의 에너지 밴드 갭을 뛰어넘고 또한 충돌에 의한 새로운 전자,정공을 형성시킨다. 이들 전자는 대부분 드레인으로 흡수되지만 일부는 게이트절연막에 포획되어 실리콘-절연막 계면에 준위를 생성시켜 스레시홀드 전압을 변화시키거나 상호 콘덕턴스를 저하시킨다.That is, carriers in the channel are accelerated by the high electric field formed near the drain as the device shortens, exceeding the energy band gap of silicon and forming new electrons and holes due to collision. Most of these electrons are absorbed by the drain, but some are trapped in the gate insulating film to create a level at the silicon-insulating film interface to change the threshold voltage or lower the mutual conductance.
따라서 핫 캐리어의 생성을 억제하기 위하여 제안된 것이 소위 LDD(lightly doped drain) 구조로서, 소오스, 드레인 영역으로부터 각기 채널영역쪽으로 저농도 영역을 형성시켜 드레인영역을 향해 이동하는 캐리어들이 두 단계의 접합과 마주치게 하여 접합표면 근처의 전계강도를 감소시키는 방안이다.Therefore, the proposed LDD (lightly doped drain) structure has been proposed to suppress the formation of hot carriers, and carriers moving toward the drain region by forming a low concentration region toward the channel region from the source and drain regions respectively face the junction of two stages. This is to reduce the field strength near the junction surface.
소위 '드레인 엔지니어링(Drain engineering)'이라고 명명되는 LDD 구조에 대한 연구는 전계강도를 가능한 줄이고, 전계강도가 최고인 지점의 위치를 게이트 엣지 하부에 위치시키고, 임팩트 이온화 지역을 실리콘 표면 아래로 깊이 밀어 넣거나, LDD 구조에 의한 기생저항의 증가를 억제시킨다는 목표 아래 다양하게 진행되어 오고 있다.(Ref. 「Silicon Processing for the VLSI Era」 S. Wolf R. N. Tauber Volume 2. 1990 pp354∼361).Research into so-called 'Drain engineering', LDD structures, reduce field strength as much as possible, position the point where the highest field strength is best beneath the gate edge, and push the impact ionization zone deep below the silicon surface, In order to suppress the increase of parasitic resistance caused by LDD structure, various progress has been made (Ref. 「Silicon Processing for the VLSI Era」 S. Wolf RN Tauber Volume 2. 1990 pp354-361).
특히 LDD 영역 전체를 게이트 하부에 위치시킴으로써 소오스·드레인과 게이트 사이의 오버랩 캐패시턴스를 증대시친 IT LDD(Inverse-T gate LDD) 구조가 1986년 T-Y. Huang, W. W. Yao 등에 의해 제안('A novel Submicron LDD transistor with inverse - T gate structure' Tech. Dig. of IEDM p.742)된 이래 IT LDD에 관하여 많은 연구가 이루어지고 있다. 오버랩된 게이트에 의해 수직전계는 공핍층의 확장을 유발하여 드레인에 의해 전계분포가 넓게 분산되었으며, 최대 전계값도 오버랩된 길이의 증가와 더불어 감소하게 되는 것이다. 그러나 상기 IT LDD 제조방법에 있어서는 n- 영역을 형성하기 위해 폴리실리콘을 50-100nm가 되도록 에칭하지만 CVD나 플라즈마 에칭의 불균일성으로 인해 폴리실리콘 에칭의 균일성이나 재현상에 한계가 존재하였다. 따라서 폴리에 대해 에칭선택비가 우수한 옥사이드나 티타늄나이트라이드(TiN)을 에칭스토퍼로 사용하는 IT LDD 제조방법이 1989년 IBM사의 D. S. Wen, C-H.Hsu 등에 의해 제안되었다.('A self-Aligned Inverse - T Gate Fully Overlapped LDD Device for Sub - Half Micron CMOS'. IEDM 89 p.765∼768)In particular, the IT-Inverse-T gate LDD (LDD) structure, which increases the overlap capacitance between the source drain and the gate by placing the entire LDD region under the gate, was described in 1986 in T-Y. Since the proposal by Huang, W. W. Yao et al. ('A novel Submicron LDD transistor with inverse-T gate structure' Tech.Dig. Of IEDM p.742), much research has been done on IT LDD. By the overlapping gate, the vertical electric field causes the depletion layer to expand, so that the electric field distribution is widely distributed by the drain, and the maximum electric field value decreases with the increase in the overlapped length. However, in the IT LDD manufacturing method, polysilicon is etched to 50-100 nm to form an n- region, but there is a limit in uniformity or reproducibility of polysilicon etching due to non-uniformity of CVD or plasma etching. Therefore, an IT LDD manufacturing method using oxide or titanium nitride (TiN) having excellent etching selectivity for poly as an etching stopper was proposed in 1989 by DS Wen and CH.Hsu of IBM ('A self-Aligned Inverse-). T Gate Fully Overlapped LDD Device for Sub-Half Micron CMOS'.IEDM 89 p.765 ~ 768)
상기한 IT LDD 제조공정을 첨부한 도면 제 1 도를 참조하여 설명하면 다음과 같다.Referring to Figure 1 attached to the above IT LDD manufacturing process as follows.
게이트산화막(12)이 100Å의 두께로 형성된 반도체기판(11)상에 얇은 폴리실리콘막(13)을 100∼500Å 정도로 데포지션한 후 산화막(14)을 약 40Å 성장시킨다. 이어서 다른 폴리실리콘막(15)을 두껍게 형성시킨후 패터닝하여 산화막(14)을 에칭스토퍼로하여 반응성이온식각에 의해 게이트전극(15)을 만들고 비소이온(AS)로 이온주입한다. 이때 비소이온은 얇게 형성된 폴리실리콘막(13)을 통과하여 저농도의 n- 영역(16)을 형성시킨다. 이어서 폴리실리콘막(17)을 300Å 이하로 데포지션하여 하부의 폴리실리콘막(13)과 상부의 폴리실리콘층(15)을 연결하고, 유전체막을 소정의 두께로 증착한 후 에치-백하여 스페이서(18)를 만든 후 이온주입하여 n- 영역(19)을 형성시킨다. LDD 영역의 길이를 결정하는 T 모양의 확장된 폭은 유전체막의 두께에 의해 조절되며, 반응성 이온 식각의 에칭스토퍼로서 TiN을 사용할 경우 TiN의 전도체이기 때문에 연결용 폴리실리콘막(17)을 사용할 필요가 없다.A thin polysilicon film 13 is deposited on the semiconductor substrate 11 having a gate oxide film 12 having a thickness of about 100 GPa to about 100 to 500 GPa, and then the oxide film 14 is grown to about 40 GPa. Subsequently, another polysilicon film 15 is formed thick and then patterned to form the gate electrode 15 by reactive ion etching using the oxide film 14 as an etching stopper, and ion implantation into arsenic ion AS. At this time, the arsenic ions pass through the thin polysilicon film 13 to form the n-region 16 having a low concentration. Subsequently, the polysilicon film 17 is deposited at 300 Å or less to connect the lower polysilicon film 13 and the upper polysilicon layer 15, and a dielectric film is deposited to a predetermined thickness and then etched back to form a spacer ( 18) is then implanted to form n-region 19. The extended width of the T-shape, which determines the length of the LDD region, is controlled by the thickness of the dielectric film, and when TiN is used as an etching stopper for reactive ion etching, it is necessary to use the connecting polysilicon film 17 because it is a conductor of TiN. none.
그러나 상기의 IT LDD 제조공정에 의하면 산화막(14)이나 TiN 등 에칭스토퍼층의 추가로 공정이 복잡할 뿐만 아니라, 폴리실리콘(13)이 노출된 상태에서 얇은 폴리실리콘막(17)을 접착하는 경우 자연발생적인 산화막(Natural Oxide)의 제거를 위해 습식에칭공정이 추가되어야 하며, 이때 결합의 가능성이 존재하는 등의 문제점이 발생한다.However, according to the above-described IT LDD manufacturing process, in addition to the addition of an oxide film 14 or an etching stopper layer such as TiN, the process is complicated and when the thin polysilicon film 17 is bonded while the polysilicon 13 is exposed. In order to remove the naturally occurring oxide (Natural Oxide), a wet etching process must be added, and there is a problem such as the possibility of bonding exists.
따라서 본 발명의 목적은 에칭스토퍼층을 사용하지 않고서도 LDD 영역의 길이를 조절하고 채널길이를 감소시켜 줄 수 있는 IT LDD 구조를 가지는 반도체장치의 제조공정의 단순화와 특성개선에 있다.Accordingly, an object of the present invention is to simplify and improve the manufacturing process of a semiconductor device having an IT LDD structure capable of adjusting the length of the LDD region and reducing the channel length without using an etching stopper layer.
상기의 목적을 달성하기 위하여, 본 발명의 IT LDD 구조를 가지는 IG FET의 제조방법에 있어서, 반도체기판상에 게이트 절연막, 제 1 전도층, 제 1 전도층보다 산화속도가 빠른 제2전도층을 각각 소정의 두께로 차례로 적층시킨 후, 식각하여 게이트를 형성시키는 제 1 공정과, 상기 게이트 상에 산화막을 형성시켜 역 T자형 게이트(inverse - T gate)를 형성시키는 제 2 공정과, 상기 산화막을 제거한 후 이온주입하여 제2전도층을 마스킹으로 하여 반도체기판 내에 저농도영역을 형성시키는 제 3 공정과, 상기 게이트상에 산화막을 형성시킨 후 식각하여 게이트 측벽에 스페이서를 형성시킨 후 이온주입하여 고농도의 소오스, 드레인영역을 형성시키는 제 4 공정을 구비함으로써 달성된다.In order to achieve the above object, in the method of manufacturing an IG FET having the IT LDD structure of the present invention, a second conductive layer having a faster oxidation rate than a gate insulating film, a first conductive layer, and a first conductive layer is formed on a semiconductor substrate. A first step of forming a gate by etching each of them in turn after a predetermined thickness, a second step of forming an inverse-T gate by forming an oxide film on the gate, and the oxide film A third step of forming a low concentration region in the semiconductor substrate by masking the second conductive layer by ion implantation after removal, and forming an oxide film on the gate and etching to form a spacer on the sidewall of the gate, followed by ion implantation This is achieved by providing a fourth step of forming a source and a drain region.
이하 본 발명의 원리가 구체화된 실시예를 첨부한 제 2 도의 (a)∼(e)를 참조하여 상세히 설명하겠다.Hereinafter, the present invention will be described in detail with reference to FIGS. 2A to 2E with the embodiments of the present invention embodied.
(a)도는 반도체기판(21) 상에 게이트절연막으로서 산화막(22)을 데포지션하고 제 1 전도층인 폴리실리콘층(23)과 제 1 전도층보다 산화속도가 빠른 제 2 전도층인 텅스텐실리사이드(WSi.24)를 연속 증착한 후 일반적인 사진식각 기술에 의해 제 1 전도층(23)과 제 2 전도층(24)으로 구성된 게이트를 형성시켜준 단면도이다. 제 1 전도층의 두께는 후속의 산화공정시 산화정도와 후속의 저농도영역 형성을 위한 이온주입 공정시 공정변수를 고려하여 설정하며, 제 2 전도층의 두께도 후속의 산화공정시 부피감소의 정도를 고려하여 설정해 준다.(a) shows the oxide film 22 as a gate insulating film on the semiconductor substrate 21, and the polysilicon layer 23 as the first conductive layer and tungsten silicide as the second conductive layer having a faster oxidation rate than the first conductive layer. (WSi.24) is a cross-sectional view of a gate formed of the first conductive layer 23 and the second conductive layer 24 by a general photolithography technique after continuous deposition. The thickness of the first conductive layer is set in consideration of the degree of oxidation in the subsequent oxidation process and the process variable in the ion implantation process for the formation of a subsequent low concentration region, and the thickness of the second conductive layer is also the degree of volume reduction in the subsequent oxidation process. Set in consideration of.
(b)도는 게이트상에 CVD 산화막을 증착하거나 열산화(Thermal Oxidation)시켜 산화막(25)이 형성된 것을 나타낸 단면도이다. 이때 주로 온도조건에 영향을 받으면서 제 1 전도층(23)보다 제 2 전도층(24)이 산화에 의한 부피감소가 빠르게 일어나 역 T자형 게이트(inverse - T gate)가 형성된다. 예컨대 810℃에서 산화시키는 경우 WSi는 폴리실리콘보다 약 4배정도 산화가 빨리 일어난다.(b) is sectional drawing which showed the oxide film 25 formed by depositing or thermally oxidizing a CVD oxide film on a gate. At this time, the second conductive layer 24 is reduced in volume by oxidation faster than the first conductive layer 23 while being mainly influenced by temperature conditions, thereby forming an inverse-T gate. For example, when oxidized at 810 ° C., WSi oxidizes about four times faster than polysilicon.
(c)도는 (b)도의 산화막(25)을 전면습식에칭을 하여 제거시킨 후 저가속, 저농도의 이온주입을 실시하여 저농도영역(27)이 형성된 것을 나타낸 단면도이다. 제 1 전도층(23)은 충분히 얇으며 제 2 전도층(24)은 마스킹 역할을 한다.(c) is a cross-sectional view showing that the low concentration region 27 is formed by removing the oxide film 25 of FIG. The first conductive layer 23 is thin enough and the second conductive layer 24 serves as a mask.
(d)도는 게이트측벽에 스페이서를 형성하기 위하여 웨이퍼 전면에 CVD 산화막(28)을 형성시킨 단면도이다.(d) is sectional drawing in which the CVD oxide film 28 was formed in the whole surface of a wafer in order to form a spacer in a gate side wall.
(e)도는 상기 CVD 산화막(28)을 에치백하여 스페이서(29)를 형성시키고 고가속, 고농도의 이온주입을 실시하여 소오스, 드레인 영역(31)을 형성시킨 단면도이다.(e) is a cross-sectional view of the source and drain regions 31 formed by etching back the CVD oxide film 28 to form the spacers 29 and implanting them at high acceleration and high concentration.
이상의 실시예에서 살펴본 바와 같이, 본 발명은 에칭스토퍼를 사용하지 않고서도 단지 산화에 의한 부피 감소속도가 다른 두 전도층을 결합하여 게이트와 소오스·드레인간의 오버랩 캐패시턴스가 큰 역 T자형 게이트를 형성시켜 공정을 단순화시켰으며, 산화시 온도조건의 조절에 따라 저농도영역의 길이를 쉽게 조절할 수 있게 하였으며, 저농도영역의 농도를 낮게 유지하며, 깊이를 얇게 형성시켜 주고 채널길이를 감소시켜 주는 등 디바이스의 미세화에 따른 스케일링에도 상당한 효과가 있다.As described in the above embodiments, the present invention combines two conductive layers having different volume reduction rates due to oxidation without using an etching stopper to form an inverted T-shaped gate having a large overlap capacitance between the gate and the source and drain. The process is simplified, and the length of the low concentration region can be easily controlled according to the temperature condition during oxidation, the concentration of the low concentration region is kept low, the depth is thinned, and the channel length is reduced. There is a significant effect on scaling as well.
또한 본 발명의 원리가 IT LDD 구조를 가지는 개별소자는 물론 각종 메모리소자등에 폭 넓게 적용된다는 것은 더 말할 나위가 없는 것이다.In addition, it goes without saying that the principle of the present invention is widely applied to various memory devices as well as individual devices having an IT LDD structure.
Claims (7)
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