KR940025371A - Conversion circuit of interlaced scan signal into sequential scan signal - Google Patents

Conversion circuit of interlaced scan signal into sequential scan signal Download PDF

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Publication number
KR940025371A
KR940025371A KR1019930006855A KR930006855A KR940025371A KR 940025371 A KR940025371 A KR 940025371A KR 1019930006855 A KR1019930006855 A KR 1019930006855A KR 930006855 A KR930006855 A KR 930006855A KR 940025371 A KR940025371 A KR 940025371A
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South Korea
Prior art keywords
video signal
scan signal
output
band filter
interlaced
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KR1019930006855A
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Korean (ko)
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KR0141107B1 (en
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이명환
유동기
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김광호
삼성전자 주식회사
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Priority to KR1019930006855A priority Critical patent/KR0141107B1/en
Publication of KR940025371A publication Critical patent/KR940025371A/en
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Publication of KR0141107B1 publication Critical patent/KR0141107B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N11/00—Colour television systems
    • H04N11/06—Transmission systems characterised by the manner in which the individual colour picture signal components are combined
    • H04N11/20—Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
    • H04N11/22—Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards in which simultaneous signals are converted into sequential signals or vice versa

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)
  • Picture Signal Circuits (AREA)

Abstract

이 발명은 비월주사된 신호를 순차주사신호로 변화 처리하는 비월주사신호의 순차회로의 변환회로에 관한 것으로서, 입력되는 영상신호의 직고역성분을 추출하는 수직대역필터(20)와, 상기 수직대역필터(20)의 출력의 이득을 조정하여 고역성분을 피킹하는 이득조정기(30)와, 상기 수직대역필터(20)의 수직고역성분을 1H 딜레이된 영상신호에서 감산하여 수직저역성분을 출력하는 감산기(40)와, 상기 이득조정기(30)의 감산기(40)의 출력을 가산하여 피킹된 원래의 영상신호를 보간부(10) 및 스위치(SW1)로 출력하는 가산기(50)로 구성되어 영상신호의 피킹 제어 및 이득 제어를 할 수 있도록 함으로써 샤프한 영상을 얻을 수 있도록 함과 동시에 노이즈 상태에서도 양호한 영상처리가 가능토록 한 것이다.The present invention relates to a conversion circuit of a sequential circuit of an interlaced scan signal, which transforms and processes an interlaced signal into a sequential scan signal, comprising: a vertical band filter 20 for extracting a linear high frequency component of an input video signal; A gain adjuster 30 for peaking the high frequency components by adjusting the gain of the output of the filter 20, and a subtractor for outputting the vertical low frequency components by subtracting the vertical high frequency components of the vertical band filter 20 from the 1H delayed video signal. And an adder 50 which adds the output of the subtractor 40 of the gain adjuster 30 to the interpolator 10 and the switch SW1 to output the picked original video signal. By enabling peaking control and gain control, a sharp image can be obtained and good image processing can be performed even in a noisy state.

Description

비월주사신호의 순차주사신호로의 변환회로Conversion circuit of interlaced scan signal into sequential scan signal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2 도는 이 발명에 다른 비월주사신호의 순차주사신호로의 처리회로의 구성 블록도, 제 3 도는 픽셀 포인트의 정의를 나타낸 도면, 제 4 도는 이 발명의 응용예를 나타낸 도면, 제 5 도는 제 2 도 이득조정기의 값(G)에 따른 전체 주파수 특성도이다.2 is a block diagram of a processing circuit of an interlaced scanning signal as a sequential scanning signal according to the present invention, FIG. 3 is a diagram showing definition of pixel points, FIG. 4 is a diagram showing an application example of the present invention, and FIG. It is the overall frequency characteristic diagram according to the value G of the 2 degree gain regulator.

Claims (5)

입력되는 영상신호를 보간하는 보간부와, 이 보간부에 의해 보간된 영상신호와 원래의 영상신호를 선택적으로 출력하는 스위치로 되어 비월주사되어 수신된 신호를 순차주사신호로 처리하는 비월주사신호의 순차주사신호로의 변환회로에 있어서, 입력되는 영상신호의 수직고역성분을 추출하는 수직대역필터와, 상기 수직대역필터에 연결되며, 이 수직대역필터의 출력의 이득을 조정하여 고역성분을 피킹하는 이득조정기와 ; 상기 수직대역필터에 연결되며, 이 수직대역필터의 수직고역성분을 1H딜레이된 영상신호에서 감산하여 수직저역성분을 출력하는 감산기와 ' 상기 이득조정기 및 감산기에 연결되며, 이 이득조정기와 감산기의 출력을 가산하여 피킹된 원래의 영상신호를 상기 보간부 및 스위치로 출력하는 가산기를 포함하여 구성되는 비월주사신호의 순차주사신호로의 변환회로.An interpolation section for interpolating an input video signal, and a switch for selectively outputting the interpolated video signal and the original video signal, and interlaced scanning signals for interlaced scanning received signals as sequential scan signals. A circuit for converting a sequential scan signal, comprising: a vertical band filter for extracting a vertical high frequency component of an input video signal, and a vertical band filter connected to the vertical band filter to adjust the gain of the output of the vertical band filter to peak a high frequency component Gain regulator; A subtractor connected to the vertical band filter and subtracting a vertical high pass component of the vertical band filter from a 1H delayed video signal to output a vertical low pass component, and connected to the gain adjuster and the subtractor. And an adder for outputting the picked original video signal to the interpolation section and the switch, to convert the interlaced scan signal into a sequential scan signal. 제 1 항에 있어서, 상기 대여통과필터(20)는, 영상신호 입력단으로부터 입력되는 영상신호를 -1/4배 증폭하는 제1 -1/4 증폭기와 ; 상기 영상신호 입력단으로부터 입력되는 영상신호를 1H 딜레이시키는 제 1 라인 메모리와 ; 상기 제 1 라인 메모리의 출력을 1/2배 증폭하는 1/2 증폭기와 ; 상기 제 1 라인 메모리의 출력을 1H 딜레이시키는 제 2 라인 메모리와 ; 상기 제 2 라인 메모리의 출력을 -1/4배 증폭하는 제2 -1/4 증폭기와 ; 상기 제1 및 제2 -1/4 증폭기와 1/2 증폭기의 출력을 가산하는 가산기로 구성되는 비월주사신호의 순차주사신호로의 변환회로.2. The rental filter of claim 1, further comprising: a first -1/4 amplifier for amplifying the video signal input from the video signal input terminal by -1/4 times; A first line memory which delays the video signal inputted from the video signal input terminal by 1H; A half amplifier for amplifying the output of the first line memory by a factor of half; A second line memory for delaying the output of the first line memory by 1H; A second -1/4 amplifier amplifying the output of the second line memory by -1/4 times; A circuit for converting interlaced scan signals into sequential scan signals comprising an adder for adding outputs of the first and second -1/4 amplifiers and 1/2 amplifiers. 제 1 항에 있어서, 별도의 노이즈 체킹 블록에서 검출된 노이즈 팩터를 이용하여 이득 조정기의 값을 노이즈에 적응적으로 변환시키도록 구성되는 비월주사신호의 순차주사신호로의 변환회로The circuit of claim 1, wherein the interlaced scan signal is converted into a progressive scan signal configured to adaptively convert a value of a gain adjuster to noise using a noise factor detected in a separate noise checking block. 제 1 항과 제 3 항에 있어서, 이득 조정기와 값은 1∼3의 범위를 갖는 것을 특징으로 하는 비월주사신호의 순차주사신호로의 변환회로.4. The circuit according to claim 1 or 3, wherein the gain adjuster and the value have a range of 1 to 3. 제 3 항에 있어서, 노이즈 성분이 많으면 이득 조정기의 값(G)를 1호하고, 노이즈 성분이 작으면 이득 조정기의 값을 3으로 하는 것을 특징으로 하는 비월주사신호의 순차주사신호로의 변환회로.4. The conversion circuit of the interlaced scan signal into a sequential scan signal according to claim 3, wherein the value G of the gain adjuster is set to 1 when there are many noise components, and the value of the gain adjuster is set to 3 when the noise component is small. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930006855A 1993-04-23 1993-04-23 Switching circuit from interlace scan to progressive scan KR0141107B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930006855A KR0141107B1 (en) 1993-04-23 1993-04-23 Switching circuit from interlace scan to progressive scan

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930006855A KR0141107B1 (en) 1993-04-23 1993-04-23 Switching circuit from interlace scan to progressive scan

Publications (2)

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KR940025371A true KR940025371A (en) 1994-11-19
KR0141107B1 KR0141107B1 (en) 1998-06-15

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