KR940017241A - Digital / Analog Converter - Google Patents

Digital / Analog Converter Download PDF

Info

Publication number
KR940017241A
KR940017241A KR1019920027308A KR920027308A KR940017241A KR 940017241 A KR940017241 A KR 940017241A KR 1019920027308 A KR1019920027308 A KR 1019920027308A KR 920027308 A KR920027308 A KR 920027308A KR 940017241 A KR940017241 A KR 940017241A
Authority
KR
South Korea
Prior art keywords
node
digital
counting means
counting
input terminal
Prior art date
Application number
KR1019920027308A
Other languages
Korean (ko)
Other versions
KR950005813B1 (en
Inventor
유희상
진태훈
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920027308A priority Critical patent/KR950005813B1/en
Publication of KR940017241A publication Critical patent/KR940017241A/en
Application granted granted Critical
Publication of KR950005813B1 publication Critical patent/KR950005813B1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/82—Digital/analogue converters with intermediate conversion to time interval
    • H03M1/822—Digital/analogue converters with intermediate conversion to time interval using pulse width modulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

본 발명은 입력데이터를 샘플링 주기마다 기억하는 기억수단과, 상기 기억수단과 노드 B와 노드 C에 연결된 앤드연산수단과, 노드 C의 반전된 신호가 입력되고 제어블럭으로 출력되고 노드 A에 연결된 카운팅 수단과, 노드 A에 입력단자가 연결되고 다른 카운팅 수단에 입출력이 각각 연결된 또다른 앤드연산수단과, 상기 노드 A,B와 두 카운팅 수단에 입력단자가 연결되고 PWM신호를 출력하는 제어블럭으로 이루어지는 것을 특징으로 한다.The present invention provides a counting means for storing input data for each sampling period, counting means connected to the node B and the node C, an inverted signal of the node C, an inverted signal of the node C, a counting block connected to the node A, and the like. Means, another end operation means connected to an input terminal at node A and input / output connected to other counting means, and a control block connected to the node A, B and two counting means at an input terminal, and outputting a PWM signal. It is characterized by.

Description

디지탈/아날로그 변환기Digital / Analog Converter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 디지탈/아날로그 변환기의 블럭 구성도, 제4도는 본 발명에 따른 PWM(Pulse Width Modulation)신호.3 is a block diagram of a digital-to-analog converter according to the present invention, and FIG. 4 is a pulse width modulation (PWM) signal according to the present invention.

Claims (2)

디지탈/아날로그 변화기에 있어서, 입력데이터를 샘플링 주기마다 기억하는 기억수단(21)과, 상기 기억수단(21)과 노드 B와 노드 C에 연결된 앤드연산수단(30)과, 노드C의 반전된 신호가 입력되고 제어블러(28)에 출력되고 노드 A에 연결된 카운팅 수단(32)과, 노드 A에 입력단자가 연결되고 카운팅 수단(33)에 입출력이 각각 연결된 앤드연산수단(31)과, 상기 노드 A,B와 두 카운팅 수단(32,33)에 입력단자가 연결되고 PWM신호를 출력하는 제어블럭으로 구성된 것을 특징으로 하는 디지탈/아날로그 변환회로.In the digital / analog changer, there are storage means 21 for storing input data at each sampling period, the end operation means 30 connected to the storage means 21, the nodes B, and the node C, and the inverted signal of the node C. And counting means 32 inputted to and outputted to the control blur 28 and connected to node A, and end-operation means 31 connected to an input terminal of node A and input and output connected to counting means 33, respectively, and the node. A / B and a digital / analog conversion circuit comprising an input terminal connected to two counting means (32, 33) and a control block for outputting a PWM signal. 제1항에 있어서, 카운팅수단(32,33)이 멀티플렉서(22)와 기억수단(23)과 증분기(26)로 구성된 것을 특징으로 하는 디지탈/아날로그 변환회로.A digital / analog conversion circuit according to claim 1, characterized in that the counting means (32, 33) consists of a multiplexer (22), a storage means (23) and an incrementer (26). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920027308A 1992-12-31 1992-12-31 D/a converter KR950005813B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920027308A KR950005813B1 (en) 1992-12-31 1992-12-31 D/a converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920027308A KR950005813B1 (en) 1992-12-31 1992-12-31 D/a converter

Publications (2)

Publication Number Publication Date
KR940017241A true KR940017241A (en) 1994-07-26
KR950005813B1 KR950005813B1 (en) 1995-05-31

Family

ID=19348458

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920027308A KR950005813B1 (en) 1992-12-31 1992-12-31 D/a converter

Country Status (1)

Country Link
KR (1) KR950005813B1 (en)

Also Published As

Publication number Publication date
KR950005813B1 (en) 1995-05-31

Similar Documents

Publication Publication Date Title
KR860009427A (en) 2-phase clock signal supply shift register type semiconductor memory device
KR880013318A (en) Switched Capacitor Filter
KR940006348A (en) D / A Inverter and A / D Inverter
KR870001709A (en) D / A Converter
KR920005506A (en) D / A converter with variable circuit parameters
KR900013727A (en) Digital / Analog Converter
KR960027364A (en) Digital Audio Signal Mixing Circuit
KR940017241A (en) Digital / Analog Converter
KR860006884A (en) Waveform shaping circuit
KR940010505A (en) Signal generator
KR930017301A (en) Pulse width modulation circuit
KR850002717A (en) D / A conversion
KR880011802A (en) Semiconductor device
KR890004233A (en) Bit sequential integration circuit
KR880003474A (en) Digital servo circuit
KR850007175A (en) PCM code decoder
KR940017242A (en) Digital / Analog Converter
KR920017374A (en) Analog-to-digital converter
KR930003568A (en) Controller
JPS54100651A (en) Pulse-width/pusle-period converter circuit
KR910020689A (en) Sampling Ratio Converter
SU1695506A1 (en) Device for smoothing of signal of digital-to-analog computer
KR920003769A (en) Surround control circuit
JPS57162185A (en) Sample holding circuit
KR920020843A (en) Noise signal cancellation circuit

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050422

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee