KR940016441A - Semiconductor package and manufacturing method - Google Patents

Semiconductor package and manufacturing method Download PDF

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KR940016441A
KR940016441A KR1019920027592A KR920027592A KR940016441A KR 940016441 A KR940016441 A KR 940016441A KR 1019920027592 A KR1019920027592 A KR 1019920027592A KR 920027592 A KR920027592 A KR 920027592A KR 940016441 A KR940016441 A KR 940016441A
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bonding
wire
chip
semiconductor
semiconductor package
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KR1019920027592A
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KR100243555B1 (en
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최종곤
임민빈
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4945—Wire connectors having connecting portions of different types on the semiconductor or solid-state body, e.g. regular and reverse stitches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

이 발명은 와이어 본딩 방법의 개선으로 루프 높이를 낮춤으로써 얇은 패키지를 실현할 수 있는 반도체 패키지 및 그 제조방법에 관한 것이다.The present invention relates to a semiconductor package capable of realizing a thin package by lowering the loop height by an improvement of the wire bonding method, and a manufacturing method thereof.

종래의 표면 실장형 패키지의 경우, 칩패드에 1차 볼본딩을 실시한 후, 2차로 내부리더상에 스티치(Stitch)본딩하여 칩패드와 내부리드간을 결선함으로써 낮은 루프높이의 실현에 한계가 있었다.In the case of the conventional surface mount type package, the first ball bonding is performed on the chip pad, and then stitch bonding is performed on the inner leader to connect the chip pad and the inner lead to the second to limit the low loop height.

이 발명은 와이어 본딩 공정을 개선한 것으로, 내부리드상에 1차 볼본딩을 실시한 후, 칩패드에 2차로 스티치본딩을 실시하여 패키지 탑면에서 와이어 루프 절곡부위까지의 길이를 50㎛ 이상 낮춤으로써 종래의 본딩장비를 이용하여 TSOP, TQFP등의 초박형패키지를 제조할 수 있다.The present invention is an improvement of the wire bonding process, by performing the first ball bonding on the inner lead, and secondly stitch bonding on the chip pad to reduce the length from the top of the package to the wire loop bent portion by 50㎛ or more Ultra thin package such as TSOP, TQFP can be manufactured by using bonding equipment.

Description

반도체 패키지 및 그 제조방법Semiconductor package and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2 도는 이 발명의 실시예에 따른 반도체 패키지의 단면도, 제 3 도는 제 2 도의 요부(A) 확대도, 제 4 도는 이 발명의 제조공정중 와이어 본딩 구조를 나타내는 사시도이다.2 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention, FIG. 3 is an enlarged view of the main portion A of FIG. 2, and FIG. 4 is a perspective view showing the wire bonding structure during the manufacturing process of the present invention.

Claims (9)

리드 프레임의 다이패드상에 접착제를 매개하여 반도체 칩이 접착되고, 상기 반도체 칩의 다수개의 칩패드와 다수개의 내부리드간은 본딩 와이어로 결선되고, 상기 본딩 와이어 접속 후에 내부리드를 포함하는 상기 반도체 칩이 중앙에 위치하도록 상기 내부리드까지 성형수지로 몰딩되며, 몰딩되지 않은 외부리들은 하향절곡되게 구성된 반도체 패키지에 있어서, 상기 본딩 와이어는 루프 높이를 낮게 하기 위하여 볼본딩이 내부리드에형성되고, 스티치 본딩이 상기 칩패드에 이루어져 있는 것을 특징으로 하는 반도체 패키지.The semiconductor chip is bonded to the die pad of the lead frame by an adhesive, and the plurality of chip pads and the plurality of inner leads of the semiconductor chip are connected by bonding wires, and the semiconductor including the inner leads after the bonding wires are connected. In a semiconductor package in which a chip is molded to the inner lead up to the inner lead, and the unmolded outer teeth are bent downward, the bonding wire is formed with a ball bonding on the inner lead to lower the loop height, and stitching. Bonding is formed on the chip pad. 제 1 항에 있어서, 상기 반도체 칩의 에지부분과 칩패드의 외곽에 와이어 새깅에 의한 단락 방지를 위한 절연물질이 코팅된 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein an insulating material is coated on edges of the semiconductor chip and an outside of the chip pad to prevent short circuit by wire sagging. 제 2 항에 있어서, 상기 절연물질은 폴리이미드(Polyimide)인 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 2, wherein the insulating material is polyimide. 제 1 항에 있어서, 상기 본딩 와이어의 재료는 Au, Cu 또는 각각의 합금들중 어느 하나인 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the bonding wire is made of Au, Cu, or an alloy thereof. 다수의 내부리드가 형성된 리드 프레임의 다이패드상에 다수개의 칩패드를 갖는 반도체 칩을 접착시키는 공정과, 캐필러리에 장착되어 있는 소정재질의 와이어의 끝단에 볼을 형성하는 공정과, 상기 내부리드상에 1차 볼본딩을 실시한 후 캐필러리를 수직상승시켰다가 수평하강을 하여 상기 칩패드에 2차로 스티치본딩을 실시하는 것을 1사이클로 본딩 해당 수만큼 반복하는 와이어 본딩공정과, 상기 반도체 칩, 와이어 및 리드 프레임을 봉합시켜 패키지 몸체를 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 패키지 제조방법.Bonding a semiconductor chip having a plurality of chip pads to a die pad of a lead frame having a plurality of inner leads, forming a ball at an end of a wire of a predetermined material attached to the capillary, and the inner lead After performing the first ball bonding on the capillary vertically and then horizontally descending to perform a second stitch bonding on the chip pad in the same cycle bonding the wire bonding process, the semiconductor chip, The method of manufacturing a semiconductor package comprising the step of forming a package body by sealing the wire and the lead frame. 제 5 항에 있어서, 다이접착 공정전에 와이어 새깅에 의한 단락 불량 방지를 위하여 상기 칩패드 주위에 절연물질을 코팅하는 공정을 더 포함하는 것을 특징으로 하는 반도체 패키지 제조방법.6. The method of claim 5, further comprising coating an insulating material around the chip pad to prevent short circuit failure by wire sagging prior to the die bonding process. 제 6 항에 있어서, 상기 절연물질은 폴리이미드(Polyimide)로 형성되는 것을 특징으로 하는 반도체 패키지 제조방법.The method of claim 6, wherein the insulating material is formed of polyimide. 제 5 항에 있어서, 스티치 본딩시 데미지를 줄이기 위하여 다이접착 공정전에 상기 칩패드에 베리어 메탈을 형성하는 공정을 더 포함하는 것을 특징으로 하는 반도체 패키지 제조방법.The method of claim 5, further comprising forming a barrier metal on the chip pad before the die bonding process in order to reduce damage during stitch bonding. 제 1 항에 있어서, 상기 와이어 본딩 공정시 와이어는 Au, Cu 또는 각각의 합금들중 어느 하나로 형성되는 것을 특징으로 하는 반도체 패키지 제조방법.The method of claim 1, wherein the wire is formed of Au, Cu, or any one of the respective alloys during the wire bonding process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920027592A 1992-12-31 1992-12-31 Semiconductor package and manufacturing method thereof KR100243555B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010035456A (en) * 2001-02-15 2001-05-07 최성규 Semiconductor light emitting package and the methods thereof
KR20040023852A (en) * 2002-09-12 2004-03-20 송기영 luminous element and manufacturing method

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100616435B1 (en) 2002-11-28 2006-08-29 삼성전자주식회사 Semiconductor package and stack package stacking the same
KR100536898B1 (en) 2003-09-04 2005-12-16 삼성전자주식회사 Wire bonding method of semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04107835A (en) * 1990-08-27 1992-04-09 Matsushita Electric Ind Co Ltd Wire bonding method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010035456A (en) * 2001-02-15 2001-05-07 최성규 Semiconductor light emitting package and the methods thereof
KR20040023852A (en) * 2002-09-12 2004-03-20 송기영 luminous element and manufacturing method

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