KR940016441A - Semiconductor package and manufacturing method - Google Patents
Semiconductor package and manufacturing method Download PDFInfo
- Publication number
- KR940016441A KR940016441A KR1019920027592A KR920027592A KR940016441A KR 940016441 A KR940016441 A KR 940016441A KR 1019920027592 A KR1019920027592 A KR 1019920027592A KR 920027592 A KR920027592 A KR 920027592A KR 940016441 A KR940016441 A KR 940016441A
- Authority
- KR
- South Korea
- Prior art keywords
- bonding
- wire
- chip
- semiconductor
- semiconductor package
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 4
- 238000000034 method Methods 0.000 claims abstract 10
- 239000011810 insulating material Substances 0.000 claims 4
- 239000004642 Polyimide Substances 0.000 claims 2
- 229910045601 alloy Inorganic materials 0.000 claims 2
- 239000000956 alloy Substances 0.000 claims 2
- 229910052802 copper Inorganic materials 0.000 claims 2
- 229910052737 gold Inorganic materials 0.000 claims 2
- 229920001721 polyimide Polymers 0.000 claims 2
- 238000007665 sagging Methods 0.000 claims 2
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 230000004888 barrier function Effects 0.000 claims 1
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4945—Wire connectors having connecting portions of different types on the semiconductor or solid-state body, e.g. regular and reverse stitches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
이 발명은 와이어 본딩 방법의 개선으로 루프 높이를 낮춤으로써 얇은 패키지를 실현할 수 있는 반도체 패키지 및 그 제조방법에 관한 것이다.The present invention relates to a semiconductor package capable of realizing a thin package by lowering the loop height by an improvement of the wire bonding method, and a manufacturing method thereof.
종래의 표면 실장형 패키지의 경우, 칩패드에 1차 볼본딩을 실시한 후, 2차로 내부리더상에 스티치(Stitch)본딩하여 칩패드와 내부리드간을 결선함으로써 낮은 루프높이의 실현에 한계가 있었다.In the case of the conventional surface mount type package, the first ball bonding is performed on the chip pad, and then stitch bonding is performed on the inner leader to connect the chip pad and the inner lead to the second to limit the low loop height.
이 발명은 와이어 본딩 공정을 개선한 것으로, 내부리드상에 1차 볼본딩을 실시한 후, 칩패드에 2차로 스티치본딩을 실시하여 패키지 탑면에서 와이어 루프 절곡부위까지의 길이를 50㎛ 이상 낮춤으로써 종래의 본딩장비를 이용하여 TSOP, TQFP등의 초박형패키지를 제조할 수 있다.The present invention is an improvement of the wire bonding process, by performing the first ball bonding on the inner lead, and secondly stitch bonding on the chip pad to reduce the length from the top of the package to the wire loop bent portion by 50㎛ or more Ultra thin package such as TSOP, TQFP can be manufactured by using bonding equipment.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제 2 도는 이 발명의 실시예에 따른 반도체 패키지의 단면도, 제 3 도는 제 2 도의 요부(A) 확대도, 제 4 도는 이 발명의 제조공정중 와이어 본딩 구조를 나타내는 사시도이다.2 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention, FIG. 3 is an enlarged view of the main portion A of FIG. 2, and FIG. 4 is a perspective view showing the wire bonding structure during the manufacturing process of the present invention.
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920027592A KR100243555B1 (en) | 1992-12-31 | 1992-12-31 | Semiconductor package and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920027592A KR100243555B1 (en) | 1992-12-31 | 1992-12-31 | Semiconductor package and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940016441A true KR940016441A (en) | 1994-07-23 |
KR100243555B1 KR100243555B1 (en) | 2000-02-01 |
Family
ID=19348792
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920027592A KR100243555B1 (en) | 1992-12-31 | 1992-12-31 | Semiconductor package and manufacturing method thereof |
Country Status (1)
Country | Link |
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KR (1) | KR100243555B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010035456A (en) * | 2001-02-15 | 2001-05-07 | 최성규 | Semiconductor light emitting package and the methods thereof |
KR20040023852A (en) * | 2002-09-12 | 2004-03-20 | 송기영 | luminous element and manufacturing method |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100616435B1 (en) | 2002-11-28 | 2006-08-29 | 삼성전자주식회사 | Semiconductor package and stack package stacking the same |
KR100536898B1 (en) | 2003-09-04 | 2005-12-16 | 삼성전자주식회사 | Wire bonding method of semiconductor device |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04107835A (en) * | 1990-08-27 | 1992-04-09 | Matsushita Electric Ind Co Ltd | Wire bonding method |
-
1992
- 1992-12-31 KR KR1019920027592A patent/KR100243555B1/en not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010035456A (en) * | 2001-02-15 | 2001-05-07 | 최성규 | Semiconductor light emitting package and the methods thereof |
KR20040023852A (en) * | 2002-09-12 | 2004-03-20 | 송기영 | luminous element and manufacturing method |
Also Published As
Publication number | Publication date |
---|---|
KR100243555B1 (en) | 2000-02-01 |
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