KR940015824A - DSP (Digital Signal Processor) Algorithm Performance Test Circuit - Google Patents
DSP (Digital Signal Processor) Algorithm Performance Test Circuit Download PDFInfo
- Publication number
- KR940015824A KR940015824A KR1019920025400A KR920025400A KR940015824A KR 940015824 A KR940015824 A KR 940015824A KR 1019920025400 A KR1019920025400 A KR 1019920025400A KR 920025400 A KR920025400 A KR 920025400A KR 940015824 A KR940015824 A KR 940015824A
- Authority
- KR
- South Korea
- Prior art keywords
- system board
- transmission
- filter
- circuit
- band filter
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Monitoring And Testing Of Exchanges (AREA)
Abstract
본 발명은 PC시스템 보드를 전화망에 연결하여 DSP 알고리즘의 성능을 시험하는 회로에 관한 것으로, 특히 CCITT V.22 bis 알고리즘의 성능시험회로에 관한 것이고, 디지탈 신호처리기와 자동이득 조절기를 갖는 PC시스템보드를 구비하여 CCITT V.22 bis 알고리즘의 성능을 시험하는 회로에 있어서, 상기 CP시스템보드의 아날로그 입력포트에 접속되어, 상기 자동이득 조절기와 함께 입력단을 통해 인가되는 수신신호의 레벨을 일정상태로 유지 시키는 가변이득 증폭기와, 상기 PC시스템보드의 아날로그 출력포트와 상기 가변이득 증폭기의 입력단에 접속되어, 모뎀이 호출상태일때 저대역 여파기가 송신경로상에 그리고 고대역 여파기는 수신경로상으로 설정되고, 모뎀이 응답상태일때 저대역 여파기는 수신경로상에 그리고 고대역 여파기는 송신경로상으로 설정되는 대역통과 여파기와, 상기 대역통과 여파기의 송신출력단에 접속되어, 송신신호의 레벨을 공중전화망에 송출가능하도록 신호레벨을 조정하는 송신출력 감쇄기와, 상기 송신출력 감쇄기의 출력단과 상기 대역통과 여파기의 수신입력단에 접속되어, 전화선과 모뎀이 접속하여 데이타 송신상태로 절환하는 선로접속부와, 상기 PC시스템보드의 디지탈 입출력 확장커넥터에 접속되어 상기 회로블럭에 제어신호를 제공하고, 아울러 데이타 단말기와 상기 PC시스템보드와의 접속을 위해 제어신호를 제공하는 제어부를 포함하는 것을 특징으로 하는 DSP 알고리즘 성능 시험회로이다.The present invention relates to a circuit for testing the performance of a DSP algorithm by connecting a PC system board to a telephone network, and more particularly, to a performance test circuit of a CCITT V.22 bis algorithm, and a PC system board having a digital signal processor and an automatic gain controller. A circuit for testing the performance of the CCITT V.22 bis algorithm, comprising: a circuit connected to an analog input port of the CP system board and maintaining a level of a received signal applied through an input terminal together with the automatic gain controller; Connected to the variable gain amplifier, the analog output port of the PC system board and the input of the variable gain amplifier, the low band filter is set on the transmission path and the high band filter is on the reception path when the modem is in a call state. When the modem is in response, the low band filter is placed on the receive path and the high band filter is placed on the transmit path. A band pass filter, a transmission output attenuator connected to a transmission output end of the band pass filter and adjusting a signal level to transmit a level of the transmission signal to a public telephone network, and an output end of the transmission output attenuator and the band pass filter. A line connection portion connected to a receiving input terminal and connected to a telephone line and a modem to switch to a data transmission state, and connected to a digital input / output extension connector of the PC system board to provide a control signal to the circuit block, and to provide a data terminal and the PC. DSP algorithm performance test circuit comprising a control unit for providing a control signal for connection to the system board.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명의 DSP 알고리즘 성능 시험회로의 기능블럭도, 제3도는 제2도의 송신출력 감쇄기의 상세회로도.2 is a functional block diagram of the DSP algorithm performance test circuit of the present invention, and FIG. 3 is a detailed circuit diagram of the transmission output attenuator of FIG.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920025400A KR940011664B1 (en) | 1992-12-24 | 1992-12-24 | Dsp algorithm performance test circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920025400A KR940011664B1 (en) | 1992-12-24 | 1992-12-24 | Dsp algorithm performance test circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940015824A true KR940015824A (en) | 1994-07-21 |
KR940011664B1 KR940011664B1 (en) | 1994-12-23 |
Family
ID=19346559
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920025400A KR940011664B1 (en) | 1992-12-24 | 1992-12-24 | Dsp algorithm performance test circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR940011664B1 (en) |
-
1992
- 1992-12-24 KR KR1019920025400A patent/KR940011664B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR940011664B1 (en) | 1994-12-23 |
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