KR940015792A - High speed addition circuit - Google Patents

High speed addition circuit Download PDF

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Publication number
KR940015792A
KR940015792A KR1019920026948A KR920026948A KR940015792A KR 940015792 A KR940015792 A KR 940015792A KR 1019920026948 A KR1019920026948 A KR 1019920026948A KR 920026948 A KR920026948 A KR 920026948A KR 940015792 A KR940015792 A KR 940015792A
Authority
KR
South Korea
Prior art keywords
mos
high speed
addition circuit
exclusive
line
Prior art date
Application number
KR1019920026948A
Other languages
Korean (ko)
Other versions
KR100265352B1 (en
Inventor
김진완
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920026948A priority Critical patent/KR100265352B1/en
Publication of KR940015792A publication Critical patent/KR940015792A/en
Application granted granted Critical
Publication of KR100265352B1 publication Critical patent/KR100265352B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Logic Circuits (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

본 발명은 X라인과 Y라인에 연결된 배타적 OR게이트, Z라인(Carry in)에 연결된 제1MOS TR, 상기 배타적 OR게이트의 출력에 연결된 인버터, 상기 인버터와 상기 Y라인에 연결된 제2MOS TR, 상기 제2MOS TR, 상기 제1MOS TR, 상기 배타적 OR게이트에 연결된 제3MOS TR을 포함하여, 상기 제2MOS TR과 제3MOS TR사이에서 캐리를 발생하도록 구성된 것을 특징으로 한다.The present invention provides an exclusive OR gate connected to an X line and a Y line, a first MOS TR connected to a Z line (Carry in), an inverter connected to an output of the exclusive OR gate, a second MOS TR connected to the inverter and the Y line, And a second MOS TR, the first MOS TR, and a third MOS TR connected to the exclusive OR gate, so as to generate a carry between the second MOS TR and the third MOS TR.

Description

고속 가산 회로High speed addition circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 가산 회로의 구성도.2 is a block diagram of an addition circuit of the present invention.

Claims (1)

X라인과 Y라인에 연결된 배타적 OR게이트, Z라인(Carry in)에 연결된 제1MOS TR, 상기 배타적 OR게이트의 출력에 연결된 인버터, 상기 인버터와 상기 Y라인에 연결된 제2MOS TR, 상기 제2MOS TR, 상기 제1MOS TR, 상기 배타적 OR게이트에 연결된 제3MOS TR을 포함하여, 상기 제2MOS TR과 제3MOS TR사이에서 캐리를 발생하도록 구성된 것을 특징으로 하는 고속 가산 회로.An exclusive OR gate connected to X and Y lines, a first MOS TR connected to a Z line (Carry in), an inverter connected to an output of the exclusive OR gate, a second MOS TR connected to the inverter and the Y line, the second MOS TR, And a third MOS TR coupled to the first MOS TR and the exclusive OR gate to generate a carry between the second MOS TR and the third MOS TR. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920026948A 1992-12-30 1992-12-30 High speed addition circuit KR100265352B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920026948A KR100265352B1 (en) 1992-12-30 1992-12-30 High speed addition circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920026948A KR100265352B1 (en) 1992-12-30 1992-12-30 High speed addition circuit

Publications (2)

Publication Number Publication Date
KR940015792A true KR940015792A (en) 1994-07-21
KR100265352B1 KR100265352B1 (en) 2000-09-15

Family

ID=19348099

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920026948A KR100265352B1 (en) 1992-12-30 1992-12-30 High speed addition circuit

Country Status (1)

Country Link
KR (1) KR100265352B1 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2071422C (en) * 1991-09-06 1996-06-25 Jack N. Shirrell Method for making prestretched film

Also Published As

Publication number Publication date
KR100265352B1 (en) 2000-09-15

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