KR940010792A - Clock multiplexing circuit - Google Patents

Clock multiplexing circuit Download PDF

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Publication number
KR940010792A
KR940010792A KR1019920020025A KR920020025A KR940010792A KR 940010792 A KR940010792 A KR 940010792A KR 1019920020025 A KR1019920020025 A KR 1019920020025A KR 920020025 A KR920020025 A KR 920020025A KR 940010792 A KR940010792 A KR 940010792A
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KR
South Korea
Prior art keywords
output
clock
selection
latching
inverted
Prior art date
Application number
KR1019920020025A
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Korean (ko)
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KR0178892B1 (en
Inventor
정준모
Original Assignee
윤종용
삼성전자 주식회사
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Application filed by 윤종용, 삼성전자 주식회사 filed Critical 윤종용
Priority to KR1019920020025A priority Critical patent/KR0178892B1/en
Publication of KR940010792A publication Critical patent/KR940010792A/en
Application granted granted Critical
Publication of KR0178892B1 publication Critical patent/KR0178892B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/67—Circuits for processing colour signals for matrixing

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Electronic Switches (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)

Abstract

본 발명은 영상신호 처리장치등의 클럭다중화 회로를 제공한다. 이러한 회로를 제공하기 위해, 본발명은 인가되는 선택신호에 응답하여 제1, 2입력중 하나를 출력하는 제1선택수단과, 클리어단을 가지며 반전된 출력을 상기 제1입력으로서 제공하고 상기 제1선택수단으로부터 인가되는 출력신호를 인가되는 클럭에 따라 래치출력하는 래치수단과, 상기 래치출력을 반전지연하는 지연수단과, 상기 지연수단의 반전지연된 출력과 제1상태를 수신하여 인가되는 상기 선택신호에 따라 어느하나를 출력하는 제2선택수단과, 클리어단을 가지며 상기 제2선택수단의 선택출력을 상기 클럭의 반전된 클럭에 따라 래치출력하여 상기 래치수단을 클리어시키는 클리어수단을 적어도 가진다.The present invention provides a clock multiplexing circuit such as an image signal processing apparatus. In order to provide such a circuit, the present invention provides a first selection means for outputting one of the first and second inputs in response to an applied selection signal, and a clear end and an inverted output as the first input. 1 latch means for latching an output signal applied from the selection means according to an applied clock, delay means for inverting the latch output, inverted delayed output of the delay means and the selection applied to receive the first state. And at least a second selection means for outputting any one according to a signal, and clearing means for clearing the latch means by latching the selection output of the second selection means in accordance with an inverted clock of the clock.

Description

클럭 다중화 회로Clock multiplexing circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따른 클럭 다중화 회로도,4 is a clock multiplexing circuit diagram according to the present invention;

제5도는 제4도의 적용에 따른 일실시예의 등가 회로도,5 is an equivalent circuit diagram of an embodiment according to the application of FIG.

제6도는 제5도의 동작 타이밍도,6 is an operation timing diagram of FIG.

제7도는 제4도의 적용에 따른 또 다른 실시예의 등가 회로도,7 is an equivalent circuit diagram of another embodiment according to the application of FIG.

제8도는 제7도의 동작 타이밍도.8 is an operation timing diagram of FIG.

Claims (4)

클럭 다중화 회로에 있어서, 인가되는 선택신호에 응답하여 제1, 2입력중 하나를 출력하는 제1선택수단과, 클리어단을 가지며 반전된 출력을 상기 제1입력으로서 제공하고 상기 제1선택수단으로부터 인가되는 출력신호를 인가되는 클럭에 따라 래치출력하는 래치수단과, 상기 래치출력을 반전지연하는 지연수단과, 상기 지연수단의 반전지연된 출력과 제1상태를 수신하여 인가되는 상기 선택신호에 따라 어느하나를 출력하는 제2선택수단과, 클리어단을 가지며 상기 제2선택수단의 선택출력을 상기 클럭의 반전된 클럭에 따라 래치출력하여 상기 래치수단을 클리어시키는 클리어수단을 가짐을 특징으로 하는 회로.A clock multiplexing circuit, comprising: first selecting means for outputting one of first and second inputs in response to an applied selection signal, and providing an inverted output having a clear end as the first input and from the first selecting means; According to the latch means for latching the output signal applied according to the applied clock, the delay means for inverting the latch output, the inverted delayed output of the delay means and the selection signal received by applying the first state. And second clearing means for outputting one, clearing means for clearing the latching means by latching the selected output of the second selecting means in accordance with an inverted clock of the clock. 제1항에 있어서, 상기 제1, 2선택수단이 멀티플렉서로 구성됨을 특징으로 하는 회로.2. A circuit according to claim 1, wherein said first and second selection means comprise a multiplexer. 제1항에 있어서, 상기 래치수단인 플립플롭으로 구성됨을 특징으로 하는 회로.2. A circuit according to claim 1, characterized in that it comprises a flip-flop which is said latching means. 제1항 또는 제3항에 있어서, 상기 지연수단이 5개의 인버터로 구성됨을 특징으로 하는 회로.4. A circuit according to claim 1 or 3, wherein said delay means comprises five inverters. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920020025A 1992-10-29 1992-10-29 Circuit for clock multiplex KR0178892B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920020025A KR0178892B1 (en) 1992-10-29 1992-10-29 Circuit for clock multiplex

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920020025A KR0178892B1 (en) 1992-10-29 1992-10-29 Circuit for clock multiplex

Publications (2)

Publication Number Publication Date
KR940010792A true KR940010792A (en) 1994-05-26
KR0178892B1 KR0178892B1 (en) 1999-05-01

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ID=19341996

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920020025A KR0178892B1 (en) 1992-10-29 1992-10-29 Circuit for clock multiplex

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KR0178892B1 (en) 1999-05-01

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