KR940009603B1 - Semiconductor package & fabricating mothod thereof - Google Patents

Semiconductor package & fabricating mothod thereof Download PDF

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Publication number
KR940009603B1
KR940009603B1 KR1019910024868A KR910024868A KR940009603B1 KR 940009603 B1 KR940009603 B1 KR 940009603B1 KR 1019910024868 A KR1019910024868 A KR 1019910024868A KR 910024868 A KR910024868 A KR 910024868A KR 940009603 B1 KR940009603 B1 KR 940009603B1
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South Korea
Prior art keywords
chip
pcb
semiconductor package
board
lead
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KR1019910024868A
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Korean (ko)
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KR930014928A (en
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권영신
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삼성전자 주식회사
김광호
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Priority to KR1019910024868A priority Critical patent/KR940009603B1/en
Publication of KR930014928A publication Critical patent/KR930014928A/en
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Publication of KR940009603B1 publication Critical patent/KR940009603B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The semiconductor package is disclosed including a PCB on which a lead pattern having a contact, a pad and a inner lead is formed, an IC chip mounted on the PCB, a chip-on-board consisting of a metal wire used for wire bonding, and a resin seal for sealing the peripherical region of the board, another chip-on-board having the same construction as that of the aforementioned chip on board, and an insertion member connecting the contacts of the chip-on-boards with each other, thereby increasing the packing density.

Description

반도체 패키지 및 그 제조방법Semiconductor package and manufacturing method

제 1 도는 종래의 반도체 패키지의 일례를 도시한 단면도.1 is a cross-sectional view showing an example of a conventional semiconductor package.

제 2a 도는 본 발명에 따른 실시예로서 수지봉합용 댐(DAM)을 설치한 패키지의 사시도.Figure 2a is a perspective view of a package provided with a resin sealing dam (DAM) as an embodiment according to the present invention.

제 2b 도는 본 발명에 따른 실시예로서 몰딩(MOLDING) 공정을 마친 반도체 패키지의 사시도.Figure 2b is a perspective view of a semiconductor package after the molding (MOLDING) process as an embodiment according to the present invention.

제 2c 도는 본 발명에 따른 실시예로서 두 칩온보오드(Chip On Board) 및 삽입부재와의 결합방법 사시도.Figure 2c is a perspective view of the coupling method between the two chip on board (Chip On Board) and the insertion member as an embodiment according to the present invention.

제 2d 도는 본 발명에 따른 실시예로서 삽입리드의 성형을 마쳐 완성된 반도체 패키지의 사시도.Figure 2d is a perspective view of a semiconductor package completed by forming the insertion lead as an embodiment according to the present invention.

본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로, 특히 리드 프레임(lead frame)을 PCB(Printed Circuit Board)로 대체하여 칩온보오드화 한 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a package and a method for manufacturing the chip on board by replacing a lead frame with a printed circuit board (PCB).

근래에 PCB에 대한 반도체 패키지의 고 실장밀도가 요구됨에 따라 실장면적을 축소시키기 위한 여러가지 반도체 패키지 및 그 제조방법이 시도되고 있다.Recently, as high package density of a semiconductor package for a PCB is required, various semiconductor packages and a method of manufacturing the same have been attempted to reduce the mounting area.

제 1 도는 종래의 일반적인 반도체 패키지를 도시한 단면도이다. IC칩(11)이 다이패드(12)위에 설치되고 IC칩(11)위의 칩패드와 내부리더(14)가 금속와이어(13)로 연결되고 그 주변부분들이 몰드수지(16)에 의해 밀폐된다. 그리고 그 외부의 양쪽으로 외부리드(15)가 나와 있는 구조로 형성된다. 상기한 종래의 반도체 패키지는 실장면에 평행하게 실장이 되는 구조이므로 실장밀도가 낮은 단점이 있다. 한편, TI(Texas Instrument)사의 수직 실장형 반도체 패키지는 실장면에 수직으로 실장되는 구조여서 상기 수평 실장형 반도체 패키지에 비해 실장밀도가 높은 장점이 있다. 그러나 상기 수직 실장형 반도체 패키지는 홀을 필요로 하는 쓰루홀(through hole) 실장방식이기 때문에 PCB 패턴의 배치공간을 축소시키는 단점이 있다.1 is a cross-sectional view showing a conventional general semiconductor package. The IC chip 11 is installed on the die pad 12, the chip pad on the IC chip 11 and the inner leader 14 are connected to the metal wire 13, and the peripheral portions thereof are sealed by the mold resin 16. do. And it is formed in a structure in which the outer lead 15 to both sides of the outside. The conventional semiconductor package described above has a disadvantage that the mounting density is low because the structure is mounted parallel to the mounting surface. On the other hand, the vertical mounting semiconductor package of Texas Instruments (TI) has a high mounting density compared to the horizontal mounting semiconductor package because it is mounted vertically on the mounting surface. However, since the vertically mounted semiconductor package has a through hole mounting method requiring holes, there is a disadvantage in that the arrangement space of the PCB pattern is reduced.

따라서 본 발명의 목적은 PCB 패턴의 배치공간을 유지할뿐 아니라 기존 수직 실장형 패키지보다 고 실장밀도를 갖는 반도체 패키지 및 그 제조방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a semiconductor package having a higher mounting density than a conventional vertically mounted package as well as maintaining a layout space of a PCB pattern and a method of manufacturing the same.

상기 목적을 달성하기 위하여 본 발명은 종래의 리드 프레임에 해당하는 패턴을 형성한 PCB에 IC칩을 설치하고 와이어 본딩을 행하고 그 주변부분을 수지봉합체로 밀폐하여 이루어진 칩온보오드와, 상기 방식으로 형성한 또 하나의 칩온보오드와, 상기 두 칩온보오드와 PCB간의 전기적 접속을 위한 삽입리드로 구성된다.In order to achieve the above object, the present invention provides a chip on board formed by installing an IC chip on a PCB having a pattern corresponding to a conventional lead frame, performing wire bonding, and sealing a peripheral portion thereof with a resin encapsulation material. Another chip on board and an insertion lead for electrical connection between the two chip on board and the PCB.

이하 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제 2a - 2d 도는 본 발명의 실시예에 따른 제조공정도로서, 제 2a 도는 수지봉합용 금형을 설치해 놓은 장치, 제 2b 도는 몰딩공정을 마쳐 칩온보오드화된 패키지, 제 2c 도는 두 칩온보오드의 결합방법 및 삽입부재와의 접속방법, 제 2d 도는 삽입리드의 성형을 마쳐 완성된 반도체 패키지의 사시도이다.2a-2d is a manufacturing process diagram according to an embodiment of the present invention, 2a is a device for installing a resin sealing mold, 2b is a chip-on-board package after the molding process, 2c is a method of joining two chip on board and 2D is a perspective view of a semiconductor package completed by molding the insertion lead.

제 2a, b 도를 참조하면 21은 리드패턴을 형성한 PCB이고, 11은 상기 PCB(21)상에 설치되는 IC칩이고, 13은 금속와이어이고, 24는 상기 금속와이어(13)에 본딩되는 내부리드이고, 22는 삽입리드와의 접속을 위한 콘택트이고, 23은 콘택트(22)와 내부리드(24)사이의 패턴이고, 26은 수지봉합용 금형이고, 27은 수지봉합체이다.Referring to FIGS. 2A and 2B, 21 is a PCB having a lead pattern, 11 is an IC chip installed on the PCB 21, 13 is a metal wire, and 24 is bonded to the metal wire 13. An inner lead, 22 is a contact for connection with the insertion lead, 23 is a pattern between the contact 22 and the inner lead 24, 26 is a resin sealing mold, and 27 is a resin sealing body.

먼저, 수직실장이 가능하도록 콘택트(22)가 한쪽 방향으로만 배치되게 내부리드(24), 패턴(23) 및 콘택트(22)를 포함한 리드패턴을 형성하여 PCB(21)를 제조한다. 상기 PCB(21) 제조에 있어서, 상기 리드패턴을 연금(soft Au)으로 0.3㎛ 이상의 두께가 되도록 도금하고 특히 상기 콘택트(22)는 삽입리드와의 접속을 위하여 소정의 넓이를 가지도록 형성한다. 상기 PCB(21)상에 다이접착제를 사용하여 IC칩(11)을 설치하고 그 IC칩(11)의 칩패드와 내부리드(24)를 와이어-본딩(wire-boding) 기술을 사용해서 금속와이어(13)로 연결한다. 그 다음 제 2b 도와 같이 상기 IC칩(11) 및 내부리드(24) 주위에 수지봉합용 댐을 접착하고 액상의 수지를 내부공간에 주입하여 봉합하거나, 댐을 접착하지 않고 에폭시등을 이용하여 트랜스퍼 몰딩(transfer molding)방법등으로 수지봉합체(27)를 형성한다. 상기 공정에 의해 제 2b 도와 같이 칩온보오드가 형성된다. 그리고 상기 공정에 의한 방식으로 또 하나의 칩온보오드를 형성한다.First, the PCB 21 is manufactured by forming a lead pattern including the inner lead 24, the pattern 23, and the contact 22 such that the contact 22 is disposed only in one direction so as to allow vertical mounting. In manufacturing the PCB 21, the lead pattern is plated to a thickness of 0.3 [mu] m or more with soft Au, and in particular, the contact 22 is formed to have a predetermined width for connection with the insertion lead. The IC chip 11 is installed on the PCB 21 using a die adhesive, and the chip pad and the inner lead 24 of the IC chip 11 are wired using a wire-boding technology. Connect with (13). Then, as shown in FIG. 2B, a resin sealing dam is attached around the IC chip 11 and the inner lead 24, and a liquid resin is injected into the inner space to be sealed or transferred using epoxy or the like without bonding the dam. The resin encapsulation body 27 is formed by a transfer molding method or the like. By the above process, the chip on board is formed as shown in FIG. 2B. Then, another chip on board is formed by the above method.

여기서 상기 두 칩온보오드 패키지가, 예를 들어 메모리카드에서 같은 뱅크(bank)에 사용되는 램(RAM)이라면 데이터를 제외한 그외 /RAS, /CAS 등의 콘트롤 신호 및 어드레스에 해당하는 콘택트는 상기 두 칩온보오드 결합시 삽입리드를 통해 공통단자가 되도록 상기 두 칩온보오드의 PCB를 설계한다.Here, if the two chip-on-board packages are, for example, RAM used in the same bank in a memory card, the contacts corresponding to the control signals and addresses of / RAS and / CAS, etc., except for data, are the two chip-on. The PCB of the two chip on boards is designed to be a common terminal through the insertion lead when bonding the board.

제 2c, d 도를 참조하면 25는 두 칩온보오드의 콘택트(22)를 PCB와 전기적으로 접속하기 위한 삽입부재이고, 25'는 상기 삽입부재(25)를 실장될 수 있는 형태로 성형한 삽입리드이다.Referring to FIGS. 2C and 2D, 25 is an insertion member for electrically connecting the contacts 22 of two chip on boards with a PCB, and 25 'is an insertion lead molded into a shape in which the insertion member 25 can be mounted. to be.

제 2c 도에서 보는 바와 같이 두 칩온보오드를 서로 반대방향이 되게 하여 겹친 뒤 상기 두 칩온보오드의 콘택트(22)에 삽입부재(25)를 끼우고 전기적 접속이 되도록 그 접속부분을 Sn/Pb으로 도금한다.As shown in FIG. 2C, the two chip on boards overlap each other in an opposite direction, and then the insertion member 25 is inserted into the contacts 22 of the two chip on boards, and the connection part is plated with Sn / Pb to make an electrical connection. do.

그 다음 마지막 공정을 제 2d 도와 같이 삽입부재(25)로 부터 Y자형 금속을 절단해 두고, 지그잭(Zig Zag) 성형하여 삽입리드(25')를 형성함으로써 반도체 패키지를 완성한다.Then, the final process is completed by cutting the Y-shaped metal from the insertion member 25 as shown in the 2d diagram, and forming the insertion lead 25 'by forming a Zig Zag to complete the semiconductor package.

상술한 바와같이 본 발명은 두 칩온 보오드 패키지가 하나의 패키지화 됨과 아울러 수직실장이 됨으로써 실장밀도를 증가시키는 효과가 있다.As described above, the present invention has the effect of increasing the mounting density by being vertically mounted while two chip-on board packages are packaged as one.

또한 표면실장이 됨으로써 쓰루홀을 필요로 하지 않기 때문에 PCB의 패턴 배치공간이 축소되지 않는 효과가 있다.In addition, since the surface mounting does not require the through hole, the pattern arrangement space of the PCB is not reduced.

Claims (4)

종래의 리드프레임을 PCB로 대체하여 이중칩온보오드화한 반도체 패키지에 있어서, 콘택트(22), 패터(23) 및 내부리드(24)를 포함한 리드패턴이 형성된 PCB(21)와, 상기 PCB(21)상에 설치된 IC칩(11)과, 와이어 본딩에 사용되는 금속와이어(13)와, 상기 주변부분들을 밀폐하는 수지봉합체(27)로 구성되는 칩온 보오드와, 상기 칩온보오드 패키지와 동일하게 구성되는 또 하나의 칩온보오드와, 상기 두 칩온보오드의 콘택트(22)를 접속하는 삽입부재(25)를 구비함을 특징으로 하는 반도체 패키지.In a semiconductor package in which a conventional lead frame is replaced with a PCB and double chip-on-boarded, a PCB 21 having a lead pattern including a contact 22, a patterner 23, and an inner lead 24 is formed, and the PCB 21 The chip-on board composed of the IC chip 11 installed on the c), the metal wire 13 used for wire bonding, and the resin encapsulation body 27 sealing the peripheral portions, and the same configuration as the chip-on-board package. And another insertion member (25) connecting the two chip on boards and the contacts (22) of the two chip on boards. 상기 반도체 패키지의 제조방법에 있어서, 콘택트(22) 및 내부리드(24)와 그 사이에 연결된 패턴(23)을 수직실장이 되도록 PCB(21)를 형성하는 공정과, 상기 PCB(21)상에 IC칩(11)을 설치하는 공정과, 상기 IC칩(11)의 패트와 내부리드(24)를 금속와이어(13)로 연결하는 와이어-본딩공정과, 수지로 IC칩(11) 주위를 밀폐하는 수지 봉합공정과, 상기 공정에 의해 형성된 두 칩온보오드 패키지를 삽입부재(25)와 함께 결합하는 공정과, 상기 삽입부재(25)로 부터 삽입리드(25')를 성형하는 공정으로 이루어지는 것을 특징으로 하는 반도체 패키지 제조방법.In the method of manufacturing the semiconductor package, the step of forming a PCB 21 to vertically mount the contact 22 and the inner lead 24 and the pattern 23 connected therebetween, and on the PCB 21 The process of installing the IC chip 11, the wire-bonding process of connecting the pad and the inner lead 24 of the IC chip 11 with the metal wires 13, and sealing the IC chip 11 with the resin. And a step of joining the two chip-on-board packages formed by the process together with the insertion member 25, and a step of forming the insertion lead 25 'from the insertion member 25. A semiconductor package manufacturing method. 제 2 항에 있어서, PCB(21)를 제조하는 공정이 콘택트(22), 패턴(23) 및 내부리드(24)가 0.3㎛ 이상의 두께가 되도록 도금하는 것을 특징으로 하는 반도체 패키지 제조방법.The method of manufacturing a semiconductor package according to claim 2, wherein the process of manufacturing the PCB (21) is plated such that the contact (22), the pattern (23) and the inner lead (24) have a thickness of 0.3 mu m or more. 제 2 항에 있어서, 삽입리드(25')를 형성하는 공정이 상기 삽입리드(25')가 표면실장이 될 수 있는 형태로 성형하는 것을 특징으로 하는 반도체 패키지 제조방법.3. A method according to claim 2, wherein the step of forming the insertion leads (25 ') is molded in such a way that the insertion leads (25') can be surface mounted.
KR1019910024868A 1991-12-28 1991-12-28 Semiconductor package & fabricating mothod thereof KR940009603B1 (en)

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KR940009603B1 true KR940009603B1 (en) 1994-10-15

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