KR940005609B1 - Method of making pattern - Google Patents
Method of making pattern Download PDFInfo
- Publication number
- KR940005609B1 KR940005609B1 KR1019910011474A KR910011474A KR940005609B1 KR 940005609 B1 KR940005609 B1 KR 940005609B1 KR 1019910011474 A KR1019910011474 A KR 1019910011474A KR 910011474 A KR910011474 A KR 910011474A KR 940005609 B1 KR940005609 B1 KR 940005609B1
- Authority
- KR
- South Korea
- Prior art keywords
- conductive layer
- layer pattern
- mask
- pattern
- insulating layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1도는 단차가 발생된 다층구조의 도전층 패턴을 도시한 단면도.1 is a cross-sectional view showing a conductive layer pattern of a multilayer structure in which a step is generated.
제2도는 종래기술에 의해 도전층 패턴을 형성한 것을 도시한 단면도.2 is a cross-sectional view showing the formation of a conductive layer pattern according to the prior art.
제3도는 본 발명의 제1실시예의 도전층 패턴을 도시한 레이아웃트도.3 is a layout diagram showing a conductive layer pattern of the first embodiment of the present invention.
제4a도 내지 제4d도는 제3도의 A-A' 단면을 본 발명에 의해 도전층 패턴을 형성하는 것은 도시한 단면도.4A to 4D are cross-sectional views illustrating the formation of a conductive layer pattern in accordance with the present invention in section A-A 'of FIG. 3;
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2, 4 ,6 : 절연층1: Substrate 2, 4, 6: Insulation layer
3, 5 및 7 : 제1, 제2 및 제3도전층 11 및 13 : 제1 및 제2절연층3, 5, and 7: first, second, and third conductive layers 11 and 13: first and second insulating layers
12 및 14 : 제1 및 제2도전층 10 및 10' : 콘택홈12 and 14: first and second conductive layers 10 and 10 ': contact groove
21 및 21' : 제1도전층 패턴 22 및 22' : 제2도전층 패턴21 and 21 ': first conductive layer pattern 22 and 22': second conductive layer pattern
23 : 제1도전층 패턴의 요홈 24 : 제1콘택마스크23: groove of the first conductive layer pattern 24: the first contact mask
25 : 제2콘택마스크25: second contact mask
본 발명은 반도체 소자의 단차가 없는 도전층 패턴 제조방법에 관한 것으로, 특히 다층구조의 배선 및 콘택구조에서 단차롤(Topology) 완화시키고 평탄화 공정을 용이하게 실시할 수 있는 단차가 없는 도전층 패턴 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a conductive layer pattern without a step of a semiconductor device. In particular, the present invention relates to a method for manufacturing a conductive layer pattern without a step that can ease a topology and facilitate a planarization process in a multi-layered wiring and contact structure. It is about a method.
일반적으로 다층구조의 반도체 소자 제조공정에서는 제1도에 도시한 바와 같이 상부에 형성하는 제3도 전층(7)을 하부의 예정된 기판(1) 영역에 콘택을 하고 예정된 형태로 패턴을 형성해야 하는데 하부에 형성된 제1 및 제2도전층(3,5)과 절연층(2,4,6)에 의해 제3도전층(7)은 심한 단차를 갖게 되고, 패턴식각시 절연층(6)의 요홈에 잔여물이 남게 된다. 따라서, 제3도전층을 형성하기 전에 하부의 절연층(6)을 평탄하게 하는 공정이 필요하게 된다.In general, in the semiconductor device manufacturing process of the multi-layer structure, as shown in FIG. 1, the third conductive layer 7 formed on the upper portion should be contacted to the lower predetermined substrate 1 region, and a pattern may be formed in a predetermined shape. The first and second conductive layers 3 and 5 and the insulating layers 2, 4 and 6 formed in the lower portion cause the third conductive layer 7 to have a severe step, and when the pattern is etched, the insulating layer 6 Residue will remain in the groove. Therefore, before forming the third conductive layer, a process of flattening the lower insulating layer 6 is required.
종래 기술에서도 상기한 바와 같은 단차등의 문제를 해결하기 위하여 평탄화 공정을 실시하였는데 예를 들어 제2도에 도시한 바와 같이 기판(1) 상부에 제1절연층(11)의 예정된 영역에 콘택홈을 형성하고 제1도전층(12)을 형성한 다음, 식각공정에 의해 패턴을 형성하면 제1도전층(12)의 두께 "a"만큼 단차가 발생한다. 따라서 제2절연층(13)을 평탄화공정으로 형성하여 콘택홈 상부에서도 원만한 굴곡을 가지도록 한 상태에서 그 상부에 제2도전층(14)을 형성하고 예정된 패턴을 형성하는데 이때에도 제2도전층(14)의 두께 "b"만큼 단차가 또 발생되어 그 상부에 제3도전층(도시안됨)을 형성할 경우 제3도전층(도시안됨) 하부에 형성하는 제3절연층을 평탄하게 형성해야 한다.In the prior art, the planarization process was performed to solve the above-described problems such as the step difference. For example, as shown in FIG. 2, a contact groove is formed in a predetermined region of the first insulating layer 11 on the substrate 1, as shown in FIG. After forming the first conductive layer 12 and forming a pattern by an etching process, a step is generated by a thickness "a" of the first conductive layer 12. Therefore, the second insulating layer 13 is formed by a planarization process to form a predetermined pattern on the upper side of the contact groove while the second conductive layer 14 is formed on the upper side of the contact groove. When a step is generated again by the thickness "b" of (14) to form a third conductive layer (not shown) on the upper part, the third insulating layer formed under the third conductive layer (not shown) should be formed flat. do.
그러나 종래기술은 도전층 패턴을 형성할 때마다 단차가 발생되어 그 상부에 형성하는 절연층을 평탄화 공정을 실시해야 하는 단점이 있다.However, the prior art has a disadvantage in that a step is generated every time the conductive layer pattern is formed, and a planarization process of the insulating layer formed thereon is performed.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 하부의 절연층을 예정된 깊이 식각하고 이 식각된 홈에 도전층 패턴을 매립하여 도전층 패턴의 높이가 하부의 절연층의 표면과 같거나 또는 조금 높게 형성하여 후에 형성되는 절연층의 평탄화공정을 제거하거나 또는 용이하게 실시할 수 있도록 한 단차가 없는 도전층 패턴 제조방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problem, the present invention etches the lower insulating layer to a predetermined depth and embeds the conductive layer pattern in the etched groove so that the height of the conductive layer pattern is equal to or slightly higher than the surface of the lower insulating layer. It is an object of the present invention to provide a method for manufacturing a conductive layer pattern without a step so that the planarization process of the insulating layer to be formed later is formed or can be easily performed.
본 발명에 의하면 기판 상부에 도전층 패턴을 형성하되 단차가 없는 도전층 패턴을 형성하기 위하여, 기판 상부에 예정된 두께의 절연층을 형성하고 도전층 패턴마스크와는 극성이 반대인 마스크를 이용하여 절연층의 소정두께를 제거한 도전층 패턴의 요홈을 형성하는 단계와, 절연층 상부에 도전층을 증착하고 도전층 패턴마스크를 이용하여 상기 도전층 패턴의 요홈에 도전층 패턴을 형성하는 것을 특징으로 한다.According to the present invention, in order to form a conductive layer pattern on the substrate, but to form a conductive layer pattern without a step, an insulating layer having a predetermined thickness is formed on the substrate and insulated using a mask having a polarity opposite to that of the conductive layer pattern mask. Forming grooves of the conductive layer pattern from which the predetermined thickness of the layer is removed; and depositing a conductive layer on the insulating layer and forming a conductive layer pattern in the grooves of the conductive layer pattern by using a conductive layer pattern mask. .
이하, 첨부된 도면을 참고하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제3도는 본 발명의 제1실시예에 의해 예정된 도전층 패턴을 도시한 레이아웃트 도면으로서, 기판 상부의 예정된 부분에 콘택되거나 또는 절연된 제1도전층 패턴(21 및 21'), 제1도전층 패턴(21 및 21')의 예정된 부분에 콘택되거나 또는 절연된 제2도전층 패턴(22 및 22')을 도시하되 제1도전층 패턴(21 및 21') 가장자리의 제1도전층 패턴의 요홈(23)은 제1전도층 패턴(21 및 21')보다 넓게 형성됨을 도시한다. 여기서 제1도전층 패턴(21 및 21')을 형성하는 마스크나 제1도전층 패턴의 요홈(23)을 형성하는 마스크는 극성이 반대인 마스크로서 실제 포토 및 식각공정을 거치게 되면 제1도전층 패턴의 요홈(23)은 폭이 넓게 되고 제1도전층 패턴(21 및 21')의 폭은 좁게 되어진다.FIG. 3 is a layout diagram showing a conductive layer pattern intended by a first embodiment of the present invention, wherein the first conductive layer patterns 21 and 21 ', the first conductive layer contacted or insulated on a predetermined portion of the upper part of the substrate, are shown in FIG. The second conductive layer patterns 22 and 22 ', which are contacted or insulated on predetermined portions of the layer patterns 21 and 21', are shown but the edges of the first conductive layer pattern at the edges of the first conductive layer patterns 21 and 21 'are shown. The recess 23 is formed to be wider than the first conductive layer patterns 21 and 21 '. Here, the mask for forming the first conductive layer patterns 21 and 21 ′ or the mask for forming the grooves 23 of the first conductive layer pattern are opposite polarities. When the photo conductive layer is subjected to the actual photo and etching processes, the first conductive layer is formed. The groove 23 of the pattern becomes wider and the width of the first conductive layer patterns 21 and 21 'becomes narrower.
제4a도 내지 제4c도는 제3도의 A-A' 단면을 도시한 것으로서 본 발명의 제조공정을 나타내었다.4A to 4C show the A-A 'cross section of FIG. 3 to show the manufacturing process of the present invention.
제4a도는 기판(1) 상부에 제1절연층(11)을 예정된 두께로 도포하고 기판(1)에 제1도전층을 콘택하기 위하여 제1콘택마스크(제3도의 24)를 이용하여 제1절연층(11)의 소정두께만 제거하여 콘택홈(10)을 형성한 상태의 단면도이다. 여기서 주지해야 할 것은 기판(1)과 제1절연층(11) 사이에는 다른 도전층 패턴 또는 절연층 패턴이 존재할 수 있으나 본 발명은 간단명료하게 설명하기 위하여 생략하였으며, 콘택홈(10) 저부의 제1절연층(11)의 일정두께 "c"를 남겨 놓는 것은 후속 제1도전층 패턴의 요홈을 형성할 때 남아 있는 콘택홈(10) 저부의 절연층(11)을 완전히 제거하여 기판(1)이 노출된 콘택홈을 형성하기 위함이다.FIG. 4A shows a first insulating layer 11 coated on the substrate 1 to a predetermined thickness and a first contact mask (24 of FIG. 3) is used to contact the first conductive layer to the substrate 1. It is sectional drawing of the state in which the contact groove 10 was formed by removing only the predetermined thickness of the insulating layer 11. It should be noted that other conductive layer patterns or insulating layer patterns may exist between the substrate 1 and the first insulating layer 11, but the present invention has been omitted for the sake of clarity and simplicity. Leaving a predetermined thickness "c" of the first insulating layer 11 completely removes the insulating layer 11 at the bottom of the contact groove 10 remaining when forming the recesses of the first conductive layer pattern. This is to form an exposed contact groove.
제4b도는 제1도전층 패턴 마스크와는 극성이 반대인 마스크를 사용하여 제1절연층(11)의 예정두께를 식각하여 제1도전층 패턴의 요홈(20)을 형성한 상태의 단면도로서, 이때 기판(1)이 노출된 콘택홈(10)도 형성된다.4B is a cross-sectional view of the groove 20 of the first conductive layer pattern formed by etching a predetermined thickness of the first insulating layer 11 using a mask having a polarity opposite to that of the first conductive layer pattern mask. In this case, the contact groove 10 in which the substrate 1 is exposed is also formed.
제4c도는 상기 제1절연층(11) 전체 상부면에 제1도전층(12A)을 증착한 다음, 제1도전층 패턴 마스크를 이용하여 제1도전층 패턴(12)을 형성한 상태의 단면도로서, 제1도전층 패턴(12)의 표면이 제1절연층(11)의 표면과 거의 같은 높이로 형성되어 있으며 제1도전층 패턴(12)은 제1도전층 패턴의 요홈(20)내에 형성됨을 도시한다.4C is a cross-sectional view of a state in which the first conductive layer 12A is formed on the entire upper surface of the first insulating layer 11 and then the first conductive layer pattern 12 is formed using the first conductive layer pattern mask. As a result, the surface of the first conductive layer pattern 12 is formed at substantially the same height as the surface of the first insulating layer 11, and the first conductive layer pattern 12 is formed in the recesses 20 of the first conductive layer pattern. It shows that it is formed.
제4d도는 제1도전층 패턴(12) 상부에 제2절연층(13)을 형성하고, 제2콘택마스크(제3도의 25)를 이용하여 제2절연층(13)의 예정된 부분이 제거된 콘택홈(10')을 형성하고 제2절연층(13) 상부에 제2도전층(14A)을 증착한 다음제2도전층 패턴마스크를 이용하여 제2도전층 패턴(14)을 형성한 상태의 단면도이다.4D illustrates a second insulating layer 13 formed on the first conductive layer pattern 12 and a predetermined portion of the second insulating layer 13 is removed by using a second contact mask (25 of FIG. 3). The contact grooves 10 'are formed, the second conductive layer 14A is deposited on the second insulating layer 13, and the second conductive layer pattern 14 is formed using the second conductive layer pattern mask. It is a cross section of.
상기한 바와 같이 본 발명에 의한 도전층 패턴의 두께만큼 단차가 발생하는 것을 방지하기 위하여 하부의 절연층을 도전층 패턴의 두께를 고려하여 소정깊이 식각한 도전층 패턴의 요홈에 도전층 패턴을 형성함으로써 그 상부에 형성하는 절연층은 평탄화 공정을 실시하지 않아도 된다.As described above, the conductive layer pattern is formed in the groove of the conductive layer pattern in which the lower insulating layer is etched a predetermined depth in consideration of the thickness of the conductive layer pattern in order to prevent the step from occurring as much as the thickness of the conductive layer pattern according to the present invention. As a result, the insulating layer formed thereon does not have to be subjected to the planarization step.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910011474A KR940005609B1 (en) | 1991-07-08 | 1991-07-08 | Method of making pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910011474A KR940005609B1 (en) | 1991-07-08 | 1991-07-08 | Method of making pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930002877A KR930002877A (en) | 1993-02-23 |
| KR940005609B1 true KR940005609B1 (en) | 1994-06-21 |
Family
ID=19316866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910011474A KR940005609B1 (en) | 1991-07-08 | 1991-07-08 | Method of making pattern |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940005609B1 (en) |
-
1991
- 1991-07-08 KR KR1019910011474A patent/KR940005609B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR930002877A (en) | 1993-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR930011781A (en) | Manufacturing method of the wiring board | |
| KR19980028939A (en) | Method for manufacturing gate electrode and gate structure manufactured accordingly | |
| KR100220297B1 (en) | Method of forming contact in mutilayered structure of semiconductor device | |
| KR940005609B1 (en) | Method of making pattern | |
| KR890011035A (en) | Integrated circuit manufacturing method and electrical connection forming method | |
| KR910000277B1 (en) | Multilayer semiconductor | |
| KR100278274B1 (en) | A method for forming stack contact in semiconductor device | |
| KR100245091B1 (en) | Process for forming interconnector of semiconductor device | |
| KR100365746B1 (en) | Method for manufacturing semiconductor device for improving contact resistance | |
| KR0179707B1 (en) | Multi-layer interconnection structure of semiconductor device and method for manufacturing thereof | |
| KR19990059099A (en) | Manufacturing Method of Semiconductor Device | |
| KR920006186B1 (en) | Method of fabricating contact hole | |
| KR100866115B1 (en) | Method for forming MIM capacitor | |
| KR950010857B1 (en) | Metalizing method of semiconductor device | |
| KR100917812B1 (en) | method for manufacturing a semiconductor device having a dual damascene | |
| KR100349365B1 (en) | Method for forming metal wiring of semiconductor device | |
| JPS6281043A (en) | Manufacture of semiconductor device | |
| KR100403323B1 (en) | Method for forming pattern of semiconductor device | |
| KR19990001665A (en) | Method for manufacturing metal wiring in semiconductor device | |
| KR960011250B1 (en) | Semiconductor contact device manufacturing method | |
| KR960008559B1 (en) | Fine contact hall forming method of semiconductor device | |
| KR910006744B1 (en) | Semiconductor contact window filling - up method | |
| KR950006340B1 (en) | Contact hole forming method of semiconductor device | |
| KR20040038139A (en) | Method of forming tungsten contact plug of semiconductor device | |
| KR19980048790A (en) | Metal contact and line formation method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| G160 | Decision to publish patent application | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20040331 Year of fee payment: 11 |
|
| LAPS | Lapse due to unpaid annual fee |