KR940004659U - 자기소거회로 - Google Patents

자기소거회로

Info

Publication number
KR940004659U
KR940004659U KR2019920012431U KR920012431U KR940004659U KR 940004659 U KR940004659 U KR 940004659U KR 2019920012431 U KR2019920012431 U KR 2019920012431U KR 920012431 U KR920012431 U KR 920012431U KR 940004659 U KR940004659 U KR 940004659U
Authority
KR
South Korea
Prior art keywords
self
erasing circuit
erasing
circuit
Prior art date
Application number
KR2019920012431U
Other languages
English (en)
Other versions
KR950009161Y1 (ko
Inventor
성일경
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR92012431U priority Critical patent/KR950009161Y1/ko
Publication of KR940004659U publication Critical patent/KR940004659U/ko
Application granted granted Critical
Publication of KR950009161Y1 publication Critical patent/KR950009161Y1/ko

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00Details of colour television systems
    • H04N9/12Picture reproducers
    • H04N9/16Picture reproducers using cathode ray tubes
    • H04N9/29Picture reproducers using cathode ray tubes using demagnetisation or compensation of external magnetic fields
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00Circuit arrangements for dc mains or dc distribution networks
    • H02J1/10Parallel operation of dc sources
    • H02J1/108Parallel operation of dc sources using diodes blocking reverse current flow
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/284Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator monostable
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H2231/00Applications
    • H01H2231/004CRT
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Video Image Reproduction Devices For Color Tv Systems (AREA)
KR92012431U 1992-07-07 1992-07-07 자기소거회로 KR950009161Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92012431U KR950009161Y1 (ko) 1992-07-07 1992-07-07 자기소거회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92012431U KR950009161Y1 (ko) 1992-07-07 1992-07-07 자기소거회로

Publications (2)

Publication Number Publication Date
KR940004659U true KR940004659U (ko) 1994-02-24
KR950009161Y1 KR950009161Y1 (ko) 1995-10-20

Family

ID=19336225

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92012431U KR950009161Y1 (ko) 1992-07-07 1992-07-07 자기소거회로

Country Status (1)

Country Link
KR (1) KR950009161Y1 (ko)

Also Published As

Publication number Publication date
KR950009161Y1 (ko) 1995-10-20

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Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 19980925

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee