KR940001152A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR940001152A
KR940001152A KR1019930009958A KR930009958A KR940001152A KR 940001152 A KR940001152 A KR 940001152A KR 1019930009958 A KR1019930009958 A KR 1019930009958A KR 930009958 A KR930009958 A KR 930009958A KR 940001152 A KR940001152 A KR 940001152A
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KR
South Korea
Prior art keywords
data
memory cell
cell arrays
address
pair
Prior art date
Application number
KR1019930009958A
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Korean (ko)
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KR0133273B1 (en
Inventor
히로끼 고이께
Original Assignee
세끼모도 다다히로
니뽄 덴끼 가부시끼가이샤
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Priority claimed from JP4142806A external-priority patent/JPH05331412A/en
Priority claimed from JP4143879A external-priority patent/JPH05342855A/en
Application filed by 세끼모도 다다히로, 니뽄 덴끼 가부시끼가이샤 filed Critical 세끼모도 다다히로
Publication of KR940001152A publication Critical patent/KR940001152A/en
Application granted granted Critical
Publication of KR0133273B1 publication Critical patent/KR0133273B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Abstract

동적 랜덤 억세스 메모리 소자는 다수의 메로리 셀 어레이(21a/21b) 사이에서 고유된 데이타 라인쌍(D7)을 가지며, 열 어드레스 디코더 유니트 (22d)는 열 선택기중의 하나가 한 관련 비트 라인쌍을 공유된 데이타 라인쌍과 결합하게 함으로써, 데이타 라인쌍은 메모리 용량과 함께 증가되지 않는다.The dynamic random access memory element has a unique data line pair D7 among a plurality of memory cell arrays 21a / 21b, and the column address decoder unit 22d shares one associated bit line pair with one of the column selectors. By combining with a pair of data line pairs, the data line pairs do not increase with memory capacity.

Description

반도체 메모리 소자Semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따른 동적 랜덤 억세스 메모리 소자의 배치를 도시한 블럭도.4 is a block diagram showing an arrangement of a dynamic random access memory device according to the present invention.

제5도는 본 발명에 따른 동적 랜덤 억세스 메모리 소자내에 포함된 열 어드레스 디코더 유니트의 배치를 도시한 논리도.5 is a logic diagram showing the arrangement of a column address decoder unit included in a dynamic random access memory element according to the present invention.

Claims (1)

a)다수의 메모리 셀 어레이 사이에서 공유되는 행 어드레스 및 열 어드레스를 제각기 할당한 다수의 어드레스 가능한 메모리 셀을 제각기 가지며, 각 블럭 어드레스를 할당한 다수의 메로리 셀 어레이, b)제1어드레스 비트에 응답하여 각 메모리 셀 어레이로부터 메모리 셀의 행을 선택하는 행 어드레싱 수단, c)다수의 메모리 셀 어레이와 제각기 결합되어, 데이타 비트를 전달하는 파수 세트의 데이타 전달 경로, d)다수의 메모리 셀 어렌이 사이에서 공유된 데이타 라인쌍, e)제2어드레스 비트에 응답하여 다수 세트의 데이타 전달 경로내에 포함된 데이타 전달경로의 하나를 선택하는 열어드레스 디코더 수단, f)다수 세트의 전달 경로 및 데이타 라인쌍 사이에 제각기 결합되고, 얼 어드레스 디코더 수단의 제어하에 전술된 한 데이타 전달 경로를 데이타 라인쌍과 결합하도록 동작하는 다수의 열 선택 수단, g)한 데이타 비트로부터 출력 데이타 신호를 발생시키는 판독 회로, h)입력 데이타 신호로부터 한 데이타 비트를 발생시키는 기록 회로와, i)판독 회로 및 기록 회로중의 하나와 데이타 라인쌍을 결합하도록 동작하는 스위칭 수단을 포함하는 반도체 메모리 소자에 있어서, 상기 데이타 전달 수단은 데이타 라인쌍(DL;OLr;Dlw)에 의해 구현되며, 상기 열 어드레스 디코더 수단은 상기 다수의 열 선택 수단이 데이타 전달 경로의 상기 다수 세트의 데이타 전달 경로중의 하나를 상기 데이타 라인쌍과 결합시키는 것을 특징으로 하는 반도체 메모리 소자.a) a plurality of memory cell arrays each having a plurality of addressable memory cells each assigned a row address and a column address shared between a plurality of memory cell arrays, b) a plurality of memory cell arrays each block address assigned, b) responding to a first address bit Row addressing means for selecting a row of memory cells from each memory cell array, c) a plurality of memory cell arrays, each coupled with a plurality of memory cell arrays, for delivering data bits, and d) between a plurality of memory cell arrays. E) open-address decoder means for selecting one of the data transfer paths contained in the plurality of data transfer paths in response to the second address bit, f) between the multiple set of transfer paths and the data line pairs. Respectively coupled to the data transmission path under the control of Earl address decoder means. A plurality of column selection means operable to couple with the in-pair, g) a readout circuit for generating an output data signal from one data bit, h) a write circuit for generating one data bit from an input data signal, and i) a readout circuit and a write circuit. A semiconductor memory device comprising switching means operative to couple one of the data line pairs with each other, wherein the data transfer means is implemented by a data line pair (DL; OLr; Dlw), and the column address decoder means comprises: And a plurality of column selection means combines one of said plurality of sets of data transfer paths of said data transfer path with said pair of data lines. ※ 참고사항：최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930009958A 1992-06-03 1993-06-03 Semiconductor memory device KR0133273B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP4142806A JPH05331412A (en) 1992-06-03 1992-06-03 Coating composition
JP92-142806 1992-06-03
JP4143879A JPH05342855A (en) 1992-06-04 1992-06-04 Semiconductor memory circuit
JP92-143879 1992-06-04

Publications (2)

Publication Number Publication Date
KR940001152A true KR940001152A (en) 1994-01-10
KR0133273B1 KR0133273B1 (en) 1998-04-16

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KR1019930009958A KR0133273B1 (en) 1992-06-03 1993-06-03 Semiconductor memory device

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