KR930018586A - Semiconductor memory device with address transition detection circuit - Google Patents

Semiconductor memory device with address transition detection circuit Download PDF

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Publication number
KR930018586A
KR930018586A KR1019930002868A KR930002868A KR930018586A KR 930018586 A KR930018586 A KR 930018586A KR 1019930002868 A KR1019930002868 A KR 1019930002868A KR 930002868 A KR930002868 A KR 930002868A KR 930018586 A KR930018586 A KR 930018586A
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South Korea
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circuit
input
signal
pulse
sum
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KR1019930002868A
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Korean (ko)
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가쓰야 나까시마
슘뻬이 고리
아끼라 나까가와라
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오가 노리오
소니 가부시기가이샤
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Publication of KR930018586A publication Critical patent/KR930018586A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Pulse Circuits (AREA)

Abstract

본 발명의 어드레스천이검출회로를 가지는 반도체메모리장치는 셋 및 리셋입력단자를 가지는 플립플롭회로(FF)와, 지연회로(3)로 구성된다. 그리고, 플립플롭회로(FF)의 셋입력단자(S)에 펄스신호를 입력하고, 플립플롭회로(FF)의 출력신호(P)는 지연회로(3)를 통해 플립플롭회로(FF)의 리셋입력단자(R)에 입력시켜서, 어드레스신호의 파형에는 의존하지 않고 어드레스의 변화에만 응답하는 일정폭의 신호를, SRAM(static random access memory)의 어드레스천이신호로서 얻도록 구성한다. SRAM의 내부회로는 일정폭의 신호에 의해 초기화되어서, 초기화시간이 어드레스신호의 파형에 의존하는 사실에 기인하는 오동작을 방지한다.The semiconductor memory device having the address transition detection circuit of the present invention is composed of a flip-flop circuit FF having a set and reset input terminal and a delay circuit 3. Then, a pulse signal is input to the set input terminal S of the flip-flop circuit FF, and the output signal P of the flip-flop circuit FF is reset of the flip-flop circuit FF through the delay circuit 3. The input terminal R is configured to obtain a signal of a constant width that does not depend on the waveform of the address signal and responds only to a change in the address as an address transition signal of the static random access memory (SRAM). The internal circuit of the SRAM is initialized by a signal of a certain width, thereby preventing malfunction due to the fact that the initialization time depends on the waveform of the address signal.

Description

어드레스천이검출회로를 가진 반도체메모리장치Semiconductor memory device with address transition detection circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명의 제1실시예에 관한 펄스발생회로의 구성을 도시한 블럭선도, 제5도는 본 발명의 제1실시예에 관한 펄스발생회로의 동작을 도시한 타이밍챠트.4 is a block diagram showing the configuration of the pulse generating circuit according to the first embodiment of the present invention, and FIG. 5 is a timing chart showing the operation of the pulse generating circuit according to the first embodiment of the present invention.

Claims (8)

플립플롭회로와, 지연회로로 이루어지고, 상기 플립플롭회로는 출력신호를 제1의 논리치로 설정하는 제어신호가 입력되는 제1의 입력단자와, 상기 출력신호를 제2의 논리치로 설정하는 제어신호가 입력되는 제2의 입력단자와, 상기 출력신호가 출력되는 출력단자를 구비하고, 상기 제1의 입력단자에는 트리거펄스신호가 입력되고, 상기 제2의 입력단자에는 상기 플립플롭회로의 출력신호를 상기 지연회로에 의해 일정시간 지연시킨 지연신호가 입력되고, 상기 출력단자에는 상기 플롭플롭회로의 출력신호가 출력회는 것을 특징으로 하는 펄스발생회로.A flip-flop circuit and a delay circuit, wherein the flip-flop circuit includes a first input terminal to which a control signal for setting an output signal as a first logic value is input, and a control for setting the output signal to a second logic value. A second input terminal to which a signal is input and an output terminal to which the output signal is output, a trigger pulse signal is input to the first input terminal, and an output of the flip-flop circuit to the second input terminal. And a delay signal for delaying a signal by the delay circuit for a predetermined time, and an output signal of the flop flop circuit is output to the output terminal. 복수의 입력단자를 구비하고, 입력신호의 합을 부여하는 수단과, 상기 제1항 기재의 펄스발생회로로 이루어지고, 이 펄스발생회로의 출력신호 및 최소한 하나의 상기 출력신호의 지연신호가 상기 입력단자에 입력되는 것을 특징으로 하는 펄스폭확대회로.Means for providing a sum of input signals and a pulse generating circuit according to claim 1, wherein the output signal of the pulse generating circuit and the delay signal of the at least one output signal are A pulse width expanding circuit, which is input to an input terminal. 복수의 입력단자를 구비하고, 입력신호의 합을 부여하는 수단과, 상기 제1항 기재의 펄스발생회로로 이루어지고, 상기 펄스발생회로의 출력신호가 상기 입력신호의 합을 부여하는 수단의 입력단자에 입력되는 것을 특징으로 하는 펄스합발생회로.Means for providing a sum of input signals, comprising a plurality of input terminals, and means for imparting a sum of the input signals to an output signal of the pulse generation circuit according to claim 1; A pulse sum generating circuit, which is input to a terminal. 복수의 입력단자를 구비하고, 입력신호의 합을 부여하는 수단과, 입력이 트리거펄스신호에 접속되는 최소한 하나의 펄스폭확대회로로 이루어지고, 이 펄스폭 확대회로의 출력신호가 상기 입력신호의 합을 부여하는 수단의 입력단자에 입력되는 것을 특징으로 하는 펄스합발생회로.Means for providing a sum of input signals, and at least one pulse width expanding circuit connected with an input of a trigger pulse signal, wherein the output signal of the pulse width expanding circuit includes a plurality of input terminals; A pulse sum generating circuit, which is input to an input terminal of a means for giving a sum. 제3항 또는 제4항에 있어서, 상기 펄스발생회로에 입력되는 트리거펄스신호는 어드레스신호의 변화에 응답하여 발생하는 어드레스천이검출신호인 것을 특징으로 하는 펄스합발생회로.The pulse sum generating circuit according to claim 3 or 4, wherein the trigger pulse signal input to the pulse generating circuit is an address transition detection signal generated in response to a change in an address signal. 복수의 어드레스선에 대응하여 접속된 어드레스천이검출회로와, 이 어드레스천이검출회로의 후단에 접속되고, 각 어드레스천이검출회로로부터의 어드레스검출호로신호의 합을 구하는 합성회로를 가지고, 상기 합성회로로부터의 출력신호에 따라서 내부회로의 리셋 또는 등화(等化)를 행하는 반도체메모리장치에 있어서, 상기 어드레스천이검출회로와 상기 합성회로의 사이에 상기 어드레스천기검출신호의 펄스폭을 일정하게 하는 펄스발생회로가 접속되어 있는 것을 특징으로 하는 반도체메모리장치.An address transition detection circuit connected to a plurality of address lines, and a synthesis circuit connected to a rear end of the address transition detection circuit and obtaining a sum of signals by an address detection arc from each address transition detection circuit. A semiconductor memory device which resets or equalizes an internal circuit in accordance with an output signal of a pulse generator, wherein the pulse generation circuit makes the pulse width of the address transition detection signal constant between the address transition detection circuit and the synthesis circuit. Is connected to the semiconductor memory device. 제6항에 있어서, 상기 펄스발생회로는 상기 어드레스천이검출신호의 입력을 유지하는 래치회로와, 이 래치회로로부터의 신호를 지연하고, 이 지연신호에 따라서 상기 래지회로를 리셋하는 지연회로를 가지는 것을 특징으로 하는 반도체메모리장치.7. The pulse generating circuit according to claim 6, wherein the pulse generating circuit comprises a latch circuit for holding an input of the address transition detection signal, a delay circuit for delaying a signal from the latch circuit, and resetting the latch circuit according to the delay signal. A semiconductor memory device comprising: 복수의 입력단자를 가지고, 입력신호의 합을 구하는 수단과, 상기 복수의 입력단자에 접속된 복수의 일정폭의 펄스발생회로와, 상기 입력신호의 합을 구하는 수단의 출력신호가 입력되는 하나의 입력단자와 레피런스전위에 접속되는 다른 입력단자를 가지는 전압비교증폭회로로 이루어지는 것을 특징으로 하는 펄스폭신장회로.A single input signal having a plurality of input terminals, a means for obtaining a sum of input signals, a plurality of pulse generators having a predetermined width connected to the plurality of input terminals, and an output signal of the means for obtaining the sum of the input signals is input. A pulse width extension circuit comprising a voltage comparison amplifier circuit having an input terminal and another input terminal connected to a reference potential. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930002868A 1992-02-28 1993-02-27 Semiconductor memory device with address transition detection circuit KR930018586A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP92-44,090 1992-02-28
JP4044090A JPH05243928A (en) 1992-02-28 1992-02-28 Pulse generation circuit, pulse width expansion circuit, and pulse sum generation circuit

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KR930018586A true KR930018586A (en) 1993-09-22

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100403610B1 (en) * 1995-11-10 2003-12-31 삼성전자주식회사 Method for resetting flip chip using delay cell

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3075164B2 (en) * 1996-01-16 2000-08-07 住友電装株式会社 Lever connector
JP5203736B2 (en) * 2008-02-07 2013-06-05 富士通株式会社 Superconducting output circuit
JP5267392B2 (en) * 2009-09-09 2013-08-21 富士電機株式会社 Pulse generation circuit and level shift circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100403610B1 (en) * 1995-11-10 2003-12-31 삼성전자주식회사 Method for resetting flip chip using delay cell

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