KR930014926A - Semiconductor package using ceramic paddle and manufacturing method - Google Patents

Semiconductor package using ceramic paddle and manufacturing method Download PDF

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Publication number
KR930014926A
KR930014926A KR1019910022693A KR910022693A KR930014926A KR 930014926 A KR930014926 A KR 930014926A KR 1019910022693 A KR1019910022693 A KR 1019910022693A KR 910022693 A KR910022693 A KR 910022693A KR 930014926 A KR930014926 A KR 930014926A
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South Korea
Prior art keywords
ceramic
paddle
chip
metal line
semiconductor package
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KR1019910022693A
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Korean (ko)
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KR100218291B1 (en
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김영선
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문정환
금성일렉트론 주식회사
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Priority to KR1019910022693A priority Critical patent/KR100218291B1/en
Publication of KR930014926A publication Critical patent/KR930014926A/en
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Publication of KR100218291B1 publication Critical patent/KR100218291B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 세라믹 패들을 이용한 반도체 패키지 및 그 제작 방법에 관한 것으로 내부에 메탈라인이 형성됨과 아울러 외부연결 단자인 복수개의 본드패드(11a)가 구비된 세라믹 패들(11)과, 그 위에 탑재되며 상기 세라믹패들(11)에 형성된 메탈라인과 접속되는 복수개의 접속패드(12a)가 구비된 반도체칩(12)과, 상기 세라믹 패들(11)에 형성된 본드패드(11a)와 연결되는 인너리드(13a)와 기판과의 접속을 위한 아웃리드(13b)가 구비된 리드프레임(13)과, 상기 칩(12)과 리드프레임(13)의 아웃리드(13b)를 포함하는 일정부위를 밀폐시키는 에폭시몰딩 컴파운드(14)로 구성됨을 특징으로 하고 있으며, 상기 세라믹 패들에는 멀티칩 또는 단독으로 사용할 칩의 마지막 메탈라인이 형성된다.The present invention relates to a semiconductor package using a ceramic paddle and a method of manufacturing the same. The ceramic paddle (11) is provided with a plurality of bond pads (11a) which are formed inside a metal line and are externally connected terminals, and are mounted thereon. A semiconductor chip 12 having a plurality of connection pads 12a connected to a metal line formed on the ceramic paddle 11 and an inner lead 13a connected to a bond pad 11a formed on the ceramic paddle 11. ) And an epoxy molding for sealing a portion including the lead frame 13 having an out lead 13b for connecting the substrate and the out lead 13b of the chip 12 and the lead frame 13. It is characterized by consisting of a compound 14, the last metal line of the chip to be used alone or multi-chip is formed in the ceramic paddle.

이와같이 된 본 발명에 의한 반도체 패키지는 집적회로 칩 제조시 메탈라인 배선공정을 쉽게 할 수 있는 효과가 있다.The semiconductor package according to the present invention as described above has an effect of facilitating a metal line wiring process in manufacturing an integrated circuit chip.

Description

세라믹 패들을 이용한 반도체 패키지 및 그 제작방법Semiconductor package using ceramic paddle and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 통상적인 반도체 패키지의 구성을 보이는 단면도,1 is a cross-sectional view showing the configuration of a conventional semiconductor package,

제2도 및 제3도는 본 발명에 의한 세라믹 패들을 이용한 반도체 패키지의 구성을 보이는 도면으로서, 제2도의 (가)(나)는 하나의 칩을 사용한 반도체 패키지의 구성을 보이는 단면도 및 (가)의 A-A선에 따른 단면도,2 and 3 are diagrams showing the configuration of a semiconductor package using a ceramic paddle according to the present invention, Figure 2 (a) (b) is a cross-sectional view showing the configuration of a semiconductor package using a single chip and (a) Section according to line AA,

제3도의 (가)(나)는 두개의 칩을 사용한 반도체 패키지의 구성을 보이는 단면도 및 (가)의 B-B선에 따른 단면도.(A) and (b) of FIG. 3 are cross-sectional views showing the structure of a semiconductor package using two chips, and a cross-sectional view along the line B-B of (a).

Claims (7)

반도체 패키지 구조에 있어서, 내부에 메탈라인이 형성됨과 아울러 외부연결단자인 복수개의 본드패드(11a)가 구비된 세라믹 패들(11)과, 그 위에 탑재되며 상기 세라믹 패들(11)에 형성된 메탈라인과 접속되는 복수개의 접속패드(12a)가 구비된 반도체칩(12)과, 상기 세라믹 패들(11)에 형성된 본드패드(11a)와 연결되는 인너리드(13a)와 기판과의 접속을 위한 아웃리드(13b)가 구비된 리드 프레임(13)과, 상기 칩(12)과 리드프레임(13)의 아웃리드(13b)를 포함하는 일정부위를 밀폐시키는 에폭시몰딩컴파운드(14)로 구성됨을 특징으로 하는 세라믹 패들을 이용한 반도체 패키지.In the semiconductor package structure, a ceramic paddle 11 having a metal line formed therein and a plurality of bond pads 11a as external connection terminals, a metal line mounted thereon, and a metal line formed on the ceramic paddle 11; A semiconductor chip 12 having a plurality of connection pads 12a connected thereto, an inner lead 13a connected to a bond pad 11a formed on the ceramic paddle 11, and an outlead for connecting the substrate ( 13b) is provided with a lead frame 13, and a ceramic, characterized in that composed of an epoxy molding compound 14 for sealing a portion including the chip 12 and the out lead (13b) of the lead frame 13 Semiconductor package using paddles. 제1항에 있어서, 상기 세라믹 패들(11)에 수개의 칩(12')(12")이 부착고정됨을 특징으로 하는 세라믹 패들을 이용한 반도체 패키지.2. The semiconductor package according to claim 1, wherein several chips (12 ') (12 ") are attached and fixed to said ceramic paddle (11). 제1항 또는 제2항에 있어서, 상기 세라믹 패들(11)에는 멀티칩(12')(12") 또는 단독으로 사용할 칩(12)의 마지막 메탈라인이 형성됨을 특징으로 하는 세라믹 패들을 이용한 반도체 패키지.The semiconductor paddle according to claim 1 or 2, wherein the ceramic paddle (11) is formed with a multi-chip (12 ') 12 "or the last metal line of the chip (12) to be used alone. package. 세라믹 패들을 이용한 반도체 패키지를 제작함에 있어서, 내부에 메탈라인이 형성되고 양변부에는 복수개의 본드패드(1a)가 구비된 세라믹 패들(11)에 복수개의 접속패드(12a)가 구비된 반도체 칩(12)을 부착고정하는 다이어태치공정과, 상기 세라믹 패드(11)의 본드패드(11a)와 리드프레임(13)의 인너리드(13a)를 전기적으로 접속, 연결시키는 본딩공정과, 상기 칩(12)과 리드프레임(13)의 아웃리드(13b)를 포함하는 일정부위를 에폭시몰딩컴파운드(14)로 밀폐시키는 몰딩공정과, 통상적인 트리밍/포밍공정 및 플래팅공정을 포함하여 제작함을 특징으로 하는 세라믹 패들을 이용한 반도체 패키지 제작방법.In manufacturing a semiconductor package using a ceramic paddle, a semiconductor chip having a plurality of connection pads 12a formed on a ceramic paddle 11 having a metal line formed therein and a plurality of bond pads 1a formed on both sides thereof ( A die attach step of attaching and fixing the 12, a bonding step of electrically connecting and connecting the bond pad 11a of the ceramic pad 11 and the inner lead 13a of the lead frame 13, and the chip 12 ) And a molding process for sealing a predetermined portion including the out lead 13b of the lead frame 13 with the epoxy molding compound 14, and a conventional trimming / forming process and a plating process. Method for manufacturing a semiconductor package using a ceramic paddle. 제4항에 있어서, 상기 세라믹 패들(11)은 세라믹 웨이퍼에 사용할 칩의 메탈라인을 형성하고, 외부연결단자인 복수개의 본드패드(11a)를 형성한 후 소정의 크기로 다이싱하여 제작함을 특징으로 하는 세라믹 패들을 이용한 반도체 패키지 제작방법.The method of claim 4, wherein the ceramic paddle 11 is formed by forming a metal line of a chip to be used in a ceramic wafer, forming a plurality of bond pads 11a, which are external connection terminals, and then dicing to a predetermined size. A semiconductor package manufacturing method using a ceramic paddle characterized in that. 제4항에 있어서, 상기 다이어태치 공정은 써모드를 이용한 가압열압착하는 방법으로 세라믹 패들(11)에 메탈라인과 반도체칩(12)의 접속패드(12a)를 상호 접속, 연결함을 특징으로 하는 세라믹 패들을 이용한 반도체 패키지 제작방법.The method of claim 4, wherein the die attach process is a method of pressurizing thermocompression bonding using a thermo mode to interconnect and connect the metal line and the connection pads 12a of the semiconductor chip 12 to the ceramic paddle 11. Method for manufacturing a semiconductor package using a ceramic paddle. 제4항에 있어서, 상기 본딩공정은 써모드를 이용하여 가압열압착하는 갱본딩 또는 금속와이어를 이용하여 전기적으로 접속, 연결시키는 와이어본딩을 포함하는 것임을 특징으로 하는 세라믹 패들을 이용한 반도체 패키지 제작방법.The method of claim 4, wherein the bonding process includes gang bonding that is pressurized and thermocompressed using a thermo mode or wire bonding that is electrically connected and connected using metal wires. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910022693A 1991-12-11 1991-12-11 Semiconductor package using a ceramic paddle and method of making same KR100218291B1 (en)

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KR1019910022693A KR100218291B1 (en) 1991-12-11 1991-12-11 Semiconductor package using a ceramic paddle and method of making same

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KR1019910022693A KR100218291B1 (en) 1991-12-11 1991-12-11 Semiconductor package using a ceramic paddle and method of making same

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KR930014926A true KR930014926A (en) 1993-07-23
KR100218291B1 KR100218291B1 (en) 1999-09-01

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KR100902766B1 (en) * 2002-09-27 2009-06-15 페어차일드코리아반도체 주식회사 Discrete package having insulated ceramic heat sink

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EP0167538B1 (en) * 1983-12-28 1989-01-18 Hughes Aircraft Company Flat package for integrated circuit memory chips

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