KR930014926A - Semiconductor package using ceramic paddle and manufacturing method - Google Patents
Semiconductor package using ceramic paddle and manufacturing method Download PDFInfo
- Publication number
- KR930014926A KR930014926A KR1019910022693A KR910022693A KR930014926A KR 930014926 A KR930014926 A KR 930014926A KR 1019910022693 A KR1019910022693 A KR 1019910022693A KR 910022693 A KR910022693 A KR 910022693A KR 930014926 A KR930014926 A KR 930014926A
- Authority
- KR
- South Korea
- Prior art keywords
- ceramic
- paddle
- chip
- metal line
- semiconductor package
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 세라믹 패들을 이용한 반도체 패키지 및 그 제작 방법에 관한 것으로 내부에 메탈라인이 형성됨과 아울러 외부연결 단자인 복수개의 본드패드(11a)가 구비된 세라믹 패들(11)과, 그 위에 탑재되며 상기 세라믹패들(11)에 형성된 메탈라인과 접속되는 복수개의 접속패드(12a)가 구비된 반도체칩(12)과, 상기 세라믹 패들(11)에 형성된 본드패드(11a)와 연결되는 인너리드(13a)와 기판과의 접속을 위한 아웃리드(13b)가 구비된 리드프레임(13)과, 상기 칩(12)과 리드프레임(13)의 아웃리드(13b)를 포함하는 일정부위를 밀폐시키는 에폭시몰딩 컴파운드(14)로 구성됨을 특징으로 하고 있으며, 상기 세라믹 패들에는 멀티칩 또는 단독으로 사용할 칩의 마지막 메탈라인이 형성된다.The present invention relates to a semiconductor package using a ceramic paddle and a method of manufacturing the same. The ceramic paddle (11) is provided with a plurality of bond pads (11a) which are formed inside a metal line and are externally connected terminals, and are mounted thereon. A semiconductor chip 12 having a plurality of connection pads 12a connected to a metal line formed on the ceramic paddle 11 and an inner lead 13a connected to a bond pad 11a formed on the ceramic paddle 11. ) And an epoxy molding for sealing a portion including the lead frame 13 having an out lead 13b for connecting the substrate and the out lead 13b of the chip 12 and the lead frame 13. It is characterized by consisting of a compound 14, the last metal line of the chip to be used alone or multi-chip is formed in the ceramic paddle.
이와같이 된 본 발명에 의한 반도체 패키지는 집적회로 칩 제조시 메탈라인 배선공정을 쉽게 할 수 있는 효과가 있다.The semiconductor package according to the present invention as described above has an effect of facilitating a metal line wiring process in manufacturing an integrated circuit chip.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 통상적인 반도체 패키지의 구성을 보이는 단면도,1 is a cross-sectional view showing the configuration of a conventional semiconductor package,
제2도 및 제3도는 본 발명에 의한 세라믹 패들을 이용한 반도체 패키지의 구성을 보이는 도면으로서, 제2도의 (가)(나)는 하나의 칩을 사용한 반도체 패키지의 구성을 보이는 단면도 및 (가)의 A-A선에 따른 단면도,2 and 3 are diagrams showing the configuration of a semiconductor package using a ceramic paddle according to the present invention, Figure 2 (a) (b) is a cross-sectional view showing the configuration of a semiconductor package using a single chip and (a) Section according to line AA,
제3도의 (가)(나)는 두개의 칩을 사용한 반도체 패키지의 구성을 보이는 단면도 및 (가)의 B-B선에 따른 단면도.(A) and (b) of FIG. 3 are cross-sectional views showing the structure of a semiconductor package using two chips, and a cross-sectional view along the line B-B of (a).
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910022693A KR100218291B1 (en) | 1991-12-11 | 1991-12-11 | Semiconductor package using a ceramic paddle and method of making same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910022693A KR100218291B1 (en) | 1991-12-11 | 1991-12-11 | Semiconductor package using a ceramic paddle and method of making same |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930014926A true KR930014926A (en) | 1993-07-23 |
KR100218291B1 KR100218291B1 (en) | 1999-09-01 |
Family
ID=19324591
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910022693A KR100218291B1 (en) | 1991-12-11 | 1991-12-11 | Semiconductor package using a ceramic paddle and method of making same |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100218291B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100902766B1 (en) * | 2002-09-27 | 2009-06-15 | 페어차일드코리아반도체 주식회사 | Discrete package having insulated ceramic heat sink |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0167538B1 (en) * | 1983-12-28 | 1989-01-18 | Hughes Aircraft Company | Flat package for integrated circuit memory chips |
-
1991
- 1991-12-11 KR KR1019910022693A patent/KR100218291B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100218291B1 (en) | 1999-09-01 |
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