KR930010672B1 - Metal etching method of semiconductor device - Google Patents
Metal etching method of semiconductor device Download PDFInfo
- Publication number
- KR930010672B1 KR930010672B1 KR1019910000404A KR910000404A KR930010672B1 KR 930010672 B1 KR930010672 B1 KR 930010672B1 KR 1019910000404 A KR1019910000404 A KR 1019910000404A KR 910000404 A KR910000404 A KR 910000404A KR 930010672 B1 KR930010672 B1 KR 930010672B1
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- South Korea
- Prior art keywords
- metal
- etching
- forming
- semiconductor device
- metal layer
- Prior art date
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- 239000002184 metal Substances 0.000 title claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 46
- 238000005530 etching Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 title abstract description 13
- 230000008021 deposition Effects 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 229920000642 polymer Polymers 0.000 description 8
- 238000010586 diagram Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
제1도는 종래의 금속식각 공정도.1 is a conventional metal etching process.
제2도는 종래의 메탈 에칭 후 상태도.2 is a state diagram after a conventional metal etching.
제3도는 본 발명에 의한 온도변환에 따른 메탈의 에칭율 특성도.3 is an etching rate characteristic of the metal according to the temperature conversion according to the present invention.
제4도는 본 발명의 금속식각 공정도.4 is a metal etching process of the present invention.
제5도는 본 발명에 따른 메탈 에칭후 상태도.5 is a state diagram after the metal etching according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2,3,4 : 금속1:
본 발명은 반도체 소자의 금속식각 방법에 관한 것으로, 특히 금속식각 공정후 진행되는 평탄화 공정을 용이하게 하고, 층간절연막형성시 발생되는 통공(viod) 형성을 억제하는데 적당한 금속의 양경사(positive slope) 에칭방법에 관한 것이다.BACKGROUND OF THE
종래에는 제1a도와 같이 반도체 기판(10) 위에 금속(20)을 형성하고 포토레지스트(PR)를 증착하고 사진석판술(photolithography)로 패터닝한다.Conventionally, as shown in FIG. 1A, the
그리고 제1b도와 같이 금속(20)을 이방성 식각에 의해 식각가스(CHF3+Cl2)를 이용하여 금속(20)을 패터닝하여 금속라인(20a)을 형성한다.As shown in FIG. 1B, the
그런데 이 공정에서 식각가스(CHF3+Cl2)를 이용하여 식각하면 처음 식각되는 금속(20)의 측면은 폴리머가 두껍게 형성되고 식각될수록 최초 형성되는 폴리머 보다 얇게 형성되므로 폴리머가 두껍게 형성되는 상부 보다 폴리머가 얇게 형성된 하측에서 식각가스에 의해 더 많이 식각되므로 금속라인(20)이 음경사(negative slope)를 갖도록 식각된다.However, in this process, when etching using the etching gas (CHF 3 + Cl 2 ), the side of the
따라서, 이와 같이 종래에는 메탈 에칭시 에칭율은 상단이나 하단이 같으나 폴리머 형상이 하단 부분에서 더 어렵기 때문에 메탈이 음경사를 형성하며, 이것은 두개의 메탈을 사용할 때나 인터메탈(Intermetal) 절연체 형성시 평탄화(planarization)에 어려움이 있으며 제2도와 같이 IMD 공정을 수행하면 통공이 형성되는 등 여러 문제점이 있었다.Thus, the conventional etching rate during metal etching is the same at the top or the bottom, but the polymer forms a penile thread because the polymer shape is more difficult at the bottom part, and this is when using two metals or when forming an intermetal insulator. There is a difficulty in planarization and there are various problems such as the formation of holes when the IMD process is performed as shown in FIG.
따라서 본 발명은 상기한 문제점을 개선시킨 것으로 제3도와 제4도 및 제5도에 의거 상세히 설명하면 다음과 같다.Therefore, the present invention improves the above problems and will be described in detail with reference to FIGS. 3 and 4 and 5 as follows.
본 발명은 제3도에 나타난 바와 같이 금속 부착시 기판온도가 고온으로 갈수록 밀도차(densification)가 높아지기 때문에 에칭율이 감소됨을 이용하여 양경사 식각을 한 것으로 제4a도와 같이 반도체 기판(1)위에 고온증착금속(2)과 저온증착금속(3)을 차례로 형성한다.According to the present invention, as shown in FIG. 3, when the metal is attached to the substrate, the densification becomes higher as the substrate temperature increases to a higher temperature. Thus, the etching rate is reduced, so that the slant etching is performed on the
여기서, 고온증착금속(2)과 저온증착금속(3)은 같은 금속을 고온에서 증착한 것이고, 저온에서 금속을 증착한 것이다.Here, the high temperature evaporation metal (2) and the low temperature evaporation metal (3) is the same metal deposited at a high temperature, the metal is deposited at a low temperature.
따라서 고온에서 증착한 금속(2)이 저온에서 증착한 금속(3)보다 에칭율이 낮게 된다.Therefore, the
그리고, 포토레지스트(PR) 마스크를 형성하고 제4b도와 같이 이방성 식각공정으로 상기 금속(2,3)층을 식각한다.Then, a photoresist (PR) mask is formed and the metal (2, 3) layer is etched by an anisotropic etching process as shown in FIG. 4b.
따라서, 금속식각시 처음 식각되는 금속측면에 폴리머가 두껍게 형성되고 식각될수록 폴리머가 얇게 형성되지만 금속(2,3)중 저온증착금속(3)보다 고온증착금속(2)이 에칭율이 낮기 때문에 양경사의 금속(4) 라인을 얻을 수 있다.Therefore, the thicker the polymer is formed on the side of the metal that is first etched during the metal etching process, the thinner the polymer is formed, but the higher the temperature of the high-temperature evaporated metal (2) than the low-temperature evaporated metal (3) among the metals (2, 3), so An
이상에서 설명한 바와 같은 본 발명은 온도변화에 따른 금속의 에칭율을 이용하여 에칭하기 때문에 양경사의 금속을 형성시킬 수 있어서 제5도와 같이 IMD를 증착해도 통공이 발생치 않고 평탄화를 원활히 할 수 있는 효과가 있다.As described above, since the present invention is etched using the etching rate of the metal according to the temperature change, it is possible to form a metal of both slopes, so that even if the IMD is deposited as shown in FIG. It works.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019910000404A KR930010672B1 (en) | 1991-01-12 | 1991-01-12 | Metal etching method of semiconductor device |
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KR1019910000404A KR930010672B1 (en) | 1991-01-12 | 1991-01-12 | Metal etching method of semiconductor device |
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KR920015469A KR920015469A (en) | 1992-08-26 |
KR930010672B1 true KR930010672B1 (en) | 1993-11-05 |
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KR1019910000404A KR930010672B1 (en) | 1991-01-12 | 1991-01-12 | Metal etching method of semiconductor device |
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1991
- 1991-01-12 KR KR1019910000404A patent/KR930010672B1/en not_active IP Right Cessation
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