KR930003288U - Data access device using DMA cycle downtime - Google Patents

Data access device using DMA cycle downtime

Info

Publication number
KR930003288U
KR930003288U KR2019910010568U KR910010568U KR930003288U KR 930003288 U KR930003288 U KR 930003288U KR 2019910010568 U KR2019910010568 U KR 2019910010568U KR 910010568 U KR910010568 U KR 910010568U KR 930003288 U KR930003288 U KR 930003288U
Authority
KR
South Korea
Prior art keywords
access device
data access
dma cycle
downtime
cycle downtime
Prior art date
Application number
KR2019910010568U
Other languages
Korean (ko)
Other versions
KR950010615Y1 (en
Inventor
안창규
Original Assignee
금성정보통신주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성정보통신주식회사 filed Critical 금성정보통신주식회사
Priority to KR2019910010568U priority Critical patent/KR950010615Y1/en
Publication of KR930003288U publication Critical patent/KR930003288U/en
Application granted granted Critical
Publication of KR950010615Y1 publication Critical patent/KR950010615Y1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
KR2019910010568U 1991-07-10 1991-07-10 Data access device using dma cycle pause period KR950010615Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019910010568U KR950010615Y1 (en) 1991-07-10 1991-07-10 Data access device using dma cycle pause period

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019910010568U KR950010615Y1 (en) 1991-07-10 1991-07-10 Data access device using dma cycle pause period

Publications (2)

Publication Number Publication Date
KR930003288U true KR930003288U (en) 1993-02-26
KR950010615Y1 KR950010615Y1 (en) 1995-12-22

Family

ID=19316263

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019910010568U KR950010615Y1 (en) 1991-07-10 1991-07-10 Data access device using dma cycle pause period

Country Status (1)

Country Link
KR (1) KR950010615Y1 (en)

Also Published As

Publication number Publication date
KR950010615Y1 (en) 1995-12-22

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Legal Events

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A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
REGI Registration of establishment
LAPS Lapse due to unpaid annual fee