KR920704344A - 반도체 플레이트(p)상호 접속 방법 및 장치 - Google Patents
반도체 플레이트(p)상호 접속 방법 및 장치Info
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- KR920704344A KR920704344A KR1019920701892A KR920701892A KR920704344A KR 920704344 A KR920704344 A KR 920704344A KR 1019920701892 A KR1019920701892 A KR 1019920701892A KR 920701892 A KR920701892 A KR 920701892A KR 920704344 A KR920704344 A KR 920704344A
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- 238000000034 method Methods 0.000 title claims description 13
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000004020 conductor Substances 0.000 claims 14
- 230000001419 dependent effect Effects 0.000 claims 3
- 230000008878 coupling Effects 0.000 claims 2
- 238000010168 coupling process Methods 0.000 claims 2
- 238000005859 coupling reaction Methods 0.000 claims 2
- 239000012212 insulator Substances 0.000 claims 2
- 239000002184 metal Substances 0.000 claims 2
- 238000001556 precipitation Methods 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000010329 laser etching Methods 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 230000001376 precipitating effect Effects 0.000 claims 1
- 230000001681 protective effect Effects 0.000 claims 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
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Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따라 반도체 플레이트의 스택의 한 실시예의 분해 사시도,
제3도는 본 발명에 따른 스택을 상호 접속시키는 방법의 제1실시예를 도시한 도면이다.
제4도는 본 발명에 따른 스택의 실용적 실시예의 단면도이다.
Claims (12)
- 각기 최소한 하나의 집적 회로 및 접속접촉면(PC)을 포함하는 반도체 플레이트(P)를 상호 접속시키는 방법으로써, 플레이트의 각 접촉면(PC)상에 전도체(F)를 접속시키는 단계(61)와, 상기 전도체가 스택면을 따라 돌출되도록 플레이트를 스태킹(62)하고 그것을 절연체(D)로 후자와 전도체(F)를 결합시키는 단계와, 최소한 이들 접속부중 몇개가 스택의 최소한 두 면상에 배열되도록 레이저의 도움으로 스택면상에 전도체(F)사이에서 전지 접속부를 형성하는 단계를 포함하는 반도체 플레이트(P)상호 접속 방법.
- 제1항에 있어서, 상기 전지 접속 형성 단계가, 모든 스택 면상에서 전도층(M)의 침전으로 이루어진 제1종속 단계(63)와, 전도체(F)와 결합하는 전지 접속부(C)를 형성하기위해 전도층의 레이저 에칭으로 이루어지는 제2종속 단계(64)를 포함하는 것을 특징으로 하는 반도체 플레이트(P)상호 접속방법.
- 제1항에 있어서, 상기 전지 접속 형성 단계가 그 위에서의 금속 침전을 유발하면서 접속부를 형성하는 표면을 레이저로 국부적으로 가열하므로써 유기 금속 증가안에서 스택을 배열하는 것으로 이루어지는 것을 특징으로 하는 반도체 플레이트(P)상호 접속 방법.
- 선행항 중 어느 한 항에 있어서, 상기 전지 접속 형성 단계동안, 소위 스택 접촉부(Pe)가 외부 회로와 스택을 접속시키기 위해 형성되고 전기 접속이 전도체(F)와 스택 접촉면(Pe)을 결합시키는 것을 특징으로 하는 반도체 플레이트(P)상호 접속 방법.
- 선행항중 어느 한 항에 있어서, 스태킹 단계 전에, 상기 플레이트를 절연 보호 물질을 커버하므로써 상기 각 플레이트를 보호하는 단계를 포함하는 것을 특징으로 하는 반도체 플레이트(P)상호 접속 방법.
- 제1항에 있어서, 상기 전기 접속부 형성 단계가, 전도체 F가 분출되는 레벨에서 스택안에 홈을 형성하는 것을 포함하므로써, 후자의 단부를 클리어하게 되는 제1종속단계(73)와, 스택 전체상에 전도층을 침전시키는 제2종속 단계(74)와, 스택의 편평한 표면으로부터 전도층을 제거하므로써, 홈안에 남게되는 제3종속 단계(75)를 포함하는 것을 특징으로 하는 반도체 플레이트(P)상호 접속 방법.
- 선행항중 어느 한 항에 있어서, 에칭 단계후, 연속적으로 최소한 전지 접속부상에서 절연층을 침전시키는 단계 및 제2층에 따라 전기 접속부를 형성하는 제2단계를 포함하는 것을 특징으로 하는 반도체 플레이트(P)상호 접속 방법.
- 각기 최소한 하나의 집적 회로와 접속 접촉부(Pc)를 포함하는 반도체 플레이트(P)를 상호 접속시키는 장치로써, 상기 플레이트(P)가 스택을 형성하도록 절연체(D)의 도움으로 서로 단단하게 이루어지고, 상기 플레이트의 접속 접촉부(Pc)가 전도체(F)에 의해 최소한 몇몇 스택면에 전기적으로 결합되며, 전도체(F)의 전기적 결합이 스택면상에서 형성된 접속부(C)에 의해 실행되고, 이들 접속부중 최소한 몇개가 스택의 최소한 두 면상에 배열되는 것을 특징으로 하는 반도체 플레이트(P)상호 접속 장치.
- 제8항에 있어서, 베이스라고 불리는 스택면중 최소한 하나가 전도체(F)를 포함하지 않으며, 상기 스택이 외부 회로와의 접속을 위해 베이스의 근처에서 그것의 표면상에 형성된 스택 접속부(PE)를 포함하고, 상기 접속부(C)가 스택 접촉부와 전도체와의 연결을 확실히 해주는 것을 특징으로 하는 반도체 플레이트(P)상호 접속방법.
- 제8항 또는 제9항에 있어서, 상기 전도체(F)가 와이어인 것을 특징으로 하는 반도체 플레이트(P)상호 접속 방법
- 제8항 또는 제9항에 있어서, 상기 전도체(F)가 스트립인 것을 특징으로 하는 반도체 플레이트(P)상호 접속 방법.
- 제10항 또는 제11항에 있어서, 상기 전도체(F)가 개별적으로 절연되는 것을 특징으로 하는 반도체 플레이트(P)상호 접속방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9015473A FR2670323B1 (fr) | 1990-12-11 | 1990-12-11 | Procede et dispositif d'interconnexion de circuits integres en trois dimensions. |
FR90/15473 | 1990-12-11 | ||
PCT/FR1991/000978 WO1992010853A1 (fr) | 1990-12-11 | 1991-12-06 | Procede et dispositif d'interconnexion de circuits integres en trois dimensions |
Publications (1)
Publication Number | Publication Date |
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KR920704344A true KR920704344A (ko) | 1992-12-19 |
Family
ID=9403101
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920701892A KR920704344A (ko) | 1990-12-11 | 1991-12-06 | 반도체 플레이트(p)상호 접속 방법 및 장치 |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP0490739B1 (ko) |
JP (1) | JP3415621B2 (ko) |
KR (1) | KR920704344A (ko) |
DE (1) | DE69126599T2 (ko) |
ES (1) | ES2104681T3 (ko) |
FR (1) | FR2670323B1 (ko) |
WO (1) | WO1992010853A1 (ko) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5847448A (en) * | 1990-12-11 | 1998-12-08 | Thomson-Csf | Method and device for interconnecting integrated circuits in three dimensions |
FR2688629A1 (fr) * | 1992-03-10 | 1993-09-17 | Thomson Csf | Procede et dispositif d'encapsulation en trois dimensions de pastilles semi-conductrices. |
FR2688630B1 (fr) * | 1992-03-13 | 2001-08-10 | Thomson Csf | Procede et dispositif d'interconnexion en trois dimensions de boitiers de composants electroniques. |
MX9305603A (es) * | 1992-09-14 | 1994-05-31 | Pierre Badehi | Metodo y aparato para producir dispositivos de circuito integrado. |
FR2696871B1 (fr) * | 1992-10-13 | 1994-11-18 | Thomson Csf | Procédé d'interconnexion 3D de boîtiers de composants électroniques, et composants 3D en résultant. |
IL106892A0 (en) * | 1993-09-02 | 1993-12-28 | Pierre Badehi | Methods and apparatus for producing integrated circuit devices |
IL108359A (en) * | 1994-01-17 | 2001-04-30 | Shellcase Ltd | Method and device for creating integrated circular devices |
US5891761A (en) * | 1994-06-23 | 1999-04-06 | Cubic Memory, Inc. | Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform |
US6080596A (en) * | 1994-06-23 | 2000-06-27 | Cubic Memory Inc. | Method for forming vertical interconnect process for silicon segments with dielectric isolation |
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US6124633A (en) * | 1994-06-23 | 2000-09-26 | Cubic Memory | Vertical interconnect process for silicon segments with thermally conductive epoxy preform |
US6255726B1 (en) | 1994-06-23 | 2001-07-03 | Cubic Memory, Inc. | Vertical interconnect process for silicon segments with dielectric isolation |
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US6624505B2 (en) | 1998-02-06 | 2003-09-23 | Shellcase, Ltd. | Packaged integrated circuits and methods of producing thereof |
IL123207A0 (en) | 1998-02-06 | 1998-09-24 | Shellcase Ltd | Integrated circuit device |
FR2785452B1 (fr) * | 1998-11-03 | 2003-06-13 | Tda Armements Sas | Procede de realisation de recepteurs d'ondes radioelectriques par interconnexion de circuits integres en trois dimensions |
FR2802706B1 (fr) | 1999-12-15 | 2002-03-01 | 3D Plus Sa | Procede et dispositif d'interconnexion en trois dimensions de composants electroniques |
KR100855015B1 (ko) | 2000-12-21 | 2008-08-28 | 테쎄라 테크놀로지스 헝가리 케이에프티. | 패키징된 집적회로 및 그 제조 방법 |
US7033664B2 (en) | 2002-10-22 | 2006-04-25 | Tessera Technologies Hungary Kft | Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby |
US7566853B2 (en) | 2005-08-12 | 2009-07-28 | Tessera, Inc. | Image sensor employing a plurality of photodetector arrays and/or rear-illuminated architecture |
US8461542B2 (en) | 2008-09-08 | 2013-06-11 | Koninklijke Philips Electronics N.V. | Radiation detector with a stack of converter plates and interconnect layers |
FR2940521B1 (fr) | 2008-12-19 | 2011-11-11 | 3D Plus | Procede de fabrication collective de modules electroniques pour montage en surface |
EP2202789A1 (en) * | 2008-12-24 | 2010-06-30 | Nxp B.V. | Stack of molded integrated circuit dies with side surface contact tracks |
JP5264640B2 (ja) * | 2009-07-24 | 2013-08-14 | 新光電気工業株式会社 | 積層型半導体装置及びその製造方法 |
RU2460171C2 (ru) * | 2010-08-23 | 2012-08-27 | Федеральное государственное унитарное предприятие Омский научно-исследовательский институт приборостроения (ФГУП ОНИИП) | Объемный модуль для радиоэлектронной аппаратуры |
DE102016104626A1 (de) | 2015-03-16 | 2016-09-22 | Jtekt Corporation | Spindelvorrichtung |
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---|---|---|---|---|
US3746934A (en) * | 1971-05-06 | 1973-07-17 | Siemens Ag | Stack arrangement of semiconductor chips |
DE2919998A1 (de) * | 1979-05-17 | 1980-11-27 | Siemens Ag | Befestigen der anschlussdraehte von halbleitersystemen auf den traegerelementen |
FR2645681B1 (fr) * | 1989-04-07 | 1994-04-08 | Thomson Csf | Dispositif d'interconnexion verticale de pastilles de circuits integres et son procede de fabrication |
-
1990
- 1990-12-11 FR FR9015473A patent/FR2670323B1/fr not_active Expired - Fee Related
-
1991
- 1991-12-06 DE DE69126599T patent/DE69126599T2/de not_active Expired - Lifetime
- 1991-12-06 EP EP91403307A patent/EP0490739B1/fr not_active Expired - Lifetime
- 1991-12-06 WO PCT/FR1991/000978 patent/WO1992010853A1/fr unknown
- 1991-12-06 ES ES91403307T patent/ES2104681T3/es not_active Expired - Lifetime
- 1991-12-06 KR KR1019920701892A patent/KR920704344A/ko active IP Right Grant
- 1991-12-06 JP JP50211392A patent/JP3415621B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69126599T2 (de) | 1997-10-02 |
FR2670323B1 (fr) | 1997-12-12 |
EP0490739B1 (fr) | 1997-06-18 |
ES2104681T3 (es) | 1997-10-16 |
EP0490739A1 (fr) | 1992-06-17 |
DE69126599D1 (de) | 1997-07-24 |
FR2670323A1 (fr) | 1992-06-12 |
JP3415621B2 (ja) | 2003-06-09 |
WO1992010853A1 (fr) | 1992-06-25 |
JPH05505067A (ja) | 1993-07-29 |
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