KR920022496A - Device Separation Method of Semiconductor Device - Google Patents

Device Separation Method of Semiconductor Device Download PDF

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Publication number
KR920022496A
KR920022496A KR1019910009059A KR910009059A KR920022496A KR 920022496 A KR920022496 A KR 920022496A KR 1019910009059 A KR1019910009059 A KR 1019910009059A KR 910009059 A KR910009059 A KR 910009059A KR 920022496 A KR920022496 A KR 920022496A
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KR
South Korea
Prior art keywords
oxide film
semiconductor substrate
nitride film
device isolation
region
Prior art date
Application number
KR1019910009059A
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Korean (ko)
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KR930010110B1 (en
Inventor
김용배
김병열
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910009059A priority Critical patent/KR930010110B1/en
Publication of KR920022496A publication Critical patent/KR920022496A/en
Application granted granted Critical
Publication of KR930010110B1 publication Critical patent/KR930010110B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)

Abstract

내용 없음.No content.

Description

반도체 장치의 소자 분리 방법Device Separation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2(A)∼(D)도는 이 발명에 따른 소자분리를 나타내는 공정도이다.2 (A) to (D) are process drawings showing device isolation according to the present invention.

Claims (3)

반도체 기판의 상부에 제1산화막 및 질화막과 제2산화막을 형성하는 공정과, 소정부분의 제2산화막, 질화막, 제1산화막 및 반도체 기판을 선택적으로 제거하여 트랜치를 형성하는 공정과, 제2산화막을 제거하고 상기 질화막과 트랜치가 형성된 반도체 기판표면에 반도체 기판과 동일한 도전형의 이온을 주입하여 이온층과 제1채널저지영역을 형성하는 공정과, 상기 질화막의 상부에 상기 트랜치가 함몰되도록 제3산화막을 도포한후 에치백에 의해 제1소자분리 영역을 형성하는 공정과, 상기 반도체 기판의 활성화 영역의 질화막 및 제1산화막을 제거하여 제2소자분리영역을 형성하는 공정과, 상기 질화막의 이온층을 활성화시켜 제2채널저지 영역을 형성하는 공정으로 이루어지는 반도체장치의 소자분리방법.Forming a first oxide film, a nitride film and a second oxide film over the semiconductor substrate, selectively removing a predetermined portion of the second oxide film, the nitride film, the first oxide film, and the semiconductor substrate to form a trench, and a second oxide film Forming a ion layer and a first channel blocking region by implanting ions of the same conductivity type as that of the semiconductor substrate on the surface of the semiconductor substrate where the nitride film and the trench are formed; Forming a first device isolation region by applying an etch back and then removing the nitride film and the first oxide film of the active region of the semiconductor substrate to form a second device isolation region, and the ion layer of the nitride film. Activating a second channel blocking region to form a second channel blocking region. 제1항에 있어서, 상기 질화막의 이온층을 희석산화법으로 활성화시키는 반도체장치의 소자분리방법.The device isolation method of claim 1, wherein the ion layer of the nitride film is activated by a dilution oxidation method. 제2항에 있어서, 상기 희석산화법의 희석가스로 N2를 사용하는 반도체 장치의 소자분리방법.The device isolation method according to claim 2, wherein N 2 is used as the dilution gas of the dilution oxidation method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910009059A 1991-05-31 1991-05-31 Isolating method of semiconductor KR930010110B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910009059A KR930010110B1 (en) 1991-05-31 1991-05-31 Isolating method of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910009059A KR930010110B1 (en) 1991-05-31 1991-05-31 Isolating method of semiconductor

Publications (2)

Publication Number Publication Date
KR920022496A true KR920022496A (en) 1992-12-19
KR930010110B1 KR930010110B1 (en) 1993-10-14

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ID=19315295

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910009059A KR930010110B1 (en) 1991-05-31 1991-05-31 Isolating method of semiconductor

Country Status (1)

Country Link
KR (1) KR930010110B1 (en)

Also Published As

Publication number Publication date
KR930010110B1 (en) 1993-10-14

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