KR920014293A - Implementation method of message transmission and reception between processes in all electronic switching system - Google Patents

Implementation method of message transmission and reception between processes in all electronic switching system Download PDF

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Publication number
KR920014293A
KR920014293A KR1019900020739A KR900020739A KR920014293A KR 920014293 A KR920014293 A KR 920014293A KR 1019900020739 A KR1019900020739 A KR 1019900020739A KR 900020739 A KR900020739 A KR 900020739A KR 920014293 A KR920014293 A KR 920014293A
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KR
South Korea
Prior art keywords
message
processing
switching system
processor unit
electronic switching
Prior art date
Application number
KR1019900020739A
Other languages
Korean (ko)
Other versions
KR930006033B1 (en
Inventor
김화성
조주현
Original Assignee
경상현
재단법인 한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 경상현, 재단법인 한국전자통신연구소 filed Critical 경상현
Priority to KR1019900020739A priority Critical patent/KR930006033B1/en
Publication of KR920014293A publication Critical patent/KR920014293A/en
Application granted granted Critical
Publication of KR930006033B1 publication Critical patent/KR930006033B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54575—Software application
    • H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Hardware Redundancy (AREA)
  • Computer And Data Communications (AREA)
  • Retry When Errors Occur (AREA)

Abstract

내용 없음No content

Description

전전자 교환 시스템에서의 프로세스간 메세지 송수신 기능 구현방법Implementation method of message transmission and reception between processes in all electronic switching system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명이 적용되는 하드웨어 시스템의 구성도, 제2도는 본 발명의 흐름도.1 is a configuration diagram of a hardware system to which the present invention is applied, and FIG. 2 is a flowchart of the present invention.

Claims (2)

다수개의 프로세서 유니트들로 구성된 대용량 전전자 교환시스템에서 동일 프로세서 유니트안에 함께 존재하는 프로세서들간의 메세지 송수신 방법과 서로 다른 프로세서 유니트에 존재하는 프로세서들간의 메세지 송수신 방법에 있어서, 초기 메세지 및 정상 메세지를 구분하여 메세지 송신요구를 하는 제1단계, 상기 제1단계 처리후 목적 프로세서 유니트의 식별자를 검사하여 프로세서 유니트안의 내부 메세지와 프로세서 유니트 외부로 나가는 외부 메세지로 구분하는 제2단계 및 상기 2단계 처리후 오류 검출 코드와 메세지 일련 번호를 생성하여 메세지에 첨부시키는 제3단계를 구비하고 있는 것을 특징으로 하는 메세지 송수신 방법.In a high-capacity electronic switching system composed of a plurality of processor units, a message is transmitted and received between processors present in the same processor unit and a message is transmitted and received between processors present in different processor units. A first step of requesting a message and an error of the second step and the second step of processing the identifier of the target processor unit after the processing of the first step, and dividing the message into an internal message in the processor unit and an external message going out of the processor unit. And a third step of generating a detection code and a message serial number and attaching the message to a message. 제1항에 있어서, 상기 제3단계 처리후 수신된 메세지에 통신 장애처리를 행하는 제4단계, 상기 제4단계후 상기 메세지가 초기 메세지인지 정상 메세지인지를 구분하는 제5단계 및 상기 제5단계 처리후 상기 초기 메세지에 대하여 목적 프로세서를 생성하는 메세지를 전달하는 제6단계를 구비하고 있는 것을 특징으로 하는 메세지 송수신 방법.4. The method of claim 1, further comprising: a fourth step of performing communication failure processing on the message received after the third step processing; a fifth step and a fifth step of discriminating whether the message is an initial message or a normal message after the fourth step; And a sixth step of delivering a message for generating a target processor with respect to the initial message after the processing. ※ 참고사항 : 최초출원내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900020739A 1990-12-15 1990-12-15 Method for transceiving messages between processors in electronic switching system KR930006033B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900020739A KR930006033B1 (en) 1990-12-15 1990-12-15 Method for transceiving messages between processors in electronic switching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900020739A KR930006033B1 (en) 1990-12-15 1990-12-15 Method for transceiving messages between processors in electronic switching system

Publications (2)

Publication Number Publication Date
KR920014293A true KR920014293A (en) 1992-07-30
KR930006033B1 KR930006033B1 (en) 1993-07-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900020739A KR930006033B1 (en) 1990-12-15 1990-12-15 Method for transceiving messages between processors in electronic switching system

Country Status (1)

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KR (1) KR930006033B1 (en)

Also Published As

Publication number Publication date
KR930006033B1 (en) 1993-07-01

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