KR920008996Y1 - Circuit for controlling contrast - Google Patents
Circuit for controlling contrast Download PDFInfo
- Publication number
- KR920008996Y1 KR920008996Y1 KR2019900008810U KR900008810U KR920008996Y1 KR 920008996 Y1 KR920008996 Y1 KR 920008996Y1 KR 2019900008810 U KR2019900008810 U KR 2019900008810U KR 900008810 U KR900008810 U KR 900008810U KR 920008996 Y1 KR920008996 Y1 KR 920008996Y1
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- South Korea
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- luminance
- circuit
- signal
- pulse
- clamp
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/57—Control of contrast or brightness
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/16—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
- H04N5/18—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Receiver Circuits (AREA)
- Picture Signal Circuits (AREA)
Abstract
내용 없음.No content.
Description
제1도는 종래의 회로도.1 is a conventional circuit diagram.
제2도는 본 고안의 블럭도.2 is a block diagram of the present invention.
제3도는 본 고안 휘도조정 회로의 상세회로도.3 is a detailed circuit diagram of the luminance adjustment circuit of the present invention.
제4도는 제2도의 각부 파형도.4 is a waveform diagram of each part of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 휘도펄스 발생회로 2 : 휘도조정 회로1: luminance pulse generating circuit 2: luminance adjusting circuit
3 : 변조회로 4 : 클램프 펄스발생회로3: modulation circuit 4: clamp pulse generating circuit
5 : 클램프회로 6 : CRT증폭회로5: clamp circuit 6: CRT amplification circuit
7 : 비교부 8 : 버퍼부7 comparison unit 8 buffer unit
R1-R16: 저항 Q1-Q4: 트랜지스터R 1 -R 16 : Resistor Q 1 -Q 4 : Transistor
C1-C4: 커패시터 VR1-VR8: 볼륨C 1 -C 4 : Capacitor VR 1 -VR 8 : Volume
본 고안은 휘도제어 회로에 관한 것으로 특히 HDTV(High Definition Television)와 같은 고해상력을 요하는 디스플레이 장치에 사용되는 휘도펄스 부가방식에 의한 휘도제어 회로에 관한 것이다.The present invention relates to a luminance control circuit, and more particularly, to a luminance control circuit using a luminance pulse addition method used in a display device requiring high resolution, such as a high definition television (HDTV).
종래에는 제1도에 나타낸 바와 같이 휘도조정용 볼륨(VR4)을 조정하여 R. G. B신호가 입력되는 영상증폭 트랜지스터(Q5)의 베이스 전압을 변화시키면 이 영상증폭 트랜지스터(Q5)는 CPT(수상관)까지 직류 결합되어 있어서 상기 베이스 전압의 변화는 CPT의 캐소우드 전압을 변화시키게 되므로 휘도가 조정되었다.Conventionally, as shown in FIG. 1, if the base voltage of the image amplifying transistor Q 5 to which the RG B signal is input is changed by adjusting the luminance adjusting volume VR 4 , the image amplifying transistor Q 5 is a CPT (number Since the change of the base voltage changes the cathode voltage of the CPT, the brightness is adjusted.
여기서 보조휘도 조정용 볼륨(VR5)은 휘도의 최대점을 결정하기 위한 것이다.In this case, the auxiliary luminance adjusting volume VR 5 is for determining the maximum point of luminance.
그러나 상기 종래기술은 영상증폭 트랜지스터(Q5)의 바이어스 전압을 가변시켜 휘도를 조정하게 되므로 이 영상증폭 트랜지스터(Q5)의 베이스로 입력되는 라인동기 신호레벨이 변하여 이러한 동기신호 레벨이 휘도조정에 영향을 주게 되는 문제점이 있었다.However, in the prior art is therefore to adjust the brightness by varying the bias voltage of the video amplifying transistor (Q 5) a line sync signal level that is input to the base of the video amplifying transistor (Q 5) is changed and this synchronization signal level is a luminance adjustment There was a problem affected.
본 고안은 상기 문제점을 해소키 위해 안출된 것으로, 입력되는 동기신호에 새롭게 휘도펄스를 부가하여 그 펄스에 따라서 직류분재생을 행하게 하므로써 동기신호 레벨의 휘도에 대한 영향을 제거할 수 있는 휘도펄스 부가방식 휘도제어 회로를 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and by adding a new luminance pulse to the input synchronous signal to perform direct current reproduction according to the pulse, the addition of a luminance pulse that can remove the influence on the luminance of the synchronous signal level. It is an object of the present invention to provide a type luminance control circuit.
이와 같은 목적을 달성하기 위한 본 고안을 첨부된 도면 제2도 내지 제4도에 의하여 상세히 설명하면 다음과 같다.The present invention for achieving the above object will be described in detail with reference to the attached drawings 2 to 4 as follows.
먼저, 제2도는 본 고안의 블록도로서 라인동기 신호를 입력으로 휘도펄스를 발생하는 휘도펄스 발생회로(1)와, 입력된 휘도펄스를 조정하여 일정폭으로 변화되는 휘도신호를 발생하는 휘도조정회로(2)와, R. G. B 입력신호를 ABL(Auto Brightness Limit) 전압과 휘도신호에 의해 변조시키는 변조회로(3)와, 라인동기 신호에 동기되어 클램프 펄스를 발생시키는 클램프 펄스발생회로(4)와, 변조회로에 의해 변도된 R. G. B 색신호를 클램프 펄스에 의해 클램프 하는 클램프 회로(5)와, 클램프 된 R. G. B 색신호를 각각 광대역으로 증폭시켜 각 R. G. B의 CPT 캐소우드에 인가하는 CPT 증폭회로(6)를 포함하여 구성된 것이다.First, FIG. 2 is a block diagram of the present invention, in which a luminance pulse generating circuit 1 generating a luminance pulse by inputting a line synchronous signal and a luminance adjustment generating a luminance signal that is changed to a predetermined width by adjusting the input luminance pulse. A circuit 2, a modulation circuit 3 for modulating the RG B input signal by an ABL (Auto Brightness Limit) voltage and a luminance signal, and a clamp pulse generation circuit 4 for generating a clamp pulse in synchronization with the line synchronization signal And a clamp circuit (5) for clamping the RG B color signal modulated by the modulation circuit with a clamp pulse, and a CPT amplifier circuit for amplifying the clamped RG B color signal in a wide band and applying it to the CPT cathode of each RG B. It is configured to include (6).
제3도는 상기 휘도조정회로(2)의 일실시예를 나타낸 것으로서, 휘도펄스 발생회로(1)로부터 출력되는 휘도펄스를 휘도조정단자에는 설정된 전압과 비교하는 트랜지스터(Q1-Q8), 저항(R9-R13)으로 된 비교부(7)와, 비교부(7)의 출력을 증폭하여 변조회로(3)에 인가하는 트랜지스터(Q4), 콘덴서(C4), 저항(R16)으로 된 버퍼부(8)를 포함하여 구성된 것이다.3 shows an embodiment of the luminance adjusting circuit 2. The transistor Q 1 -Q 8 , which compares the luminance pulse output from the luminance pulse generating circuit 1 with the set voltage at the luminance adjusting terminal, is a resistor. A comparator 7 comprising (R 9 -R 13 ), a transistor (Q 4 ), a capacitor (C 4 ), and a resistor (R 16 ) for amplifying the output of the comparator (7) and applying it to the modulation circuit (3). It is configured to include a buffer unit 8 of).
이와 같이 구성된 본 고안은 먼저 휘도펄스 발생회로(1)에서 라인 동기신호를 입력으로 하여 제4도의 (a)와 같은 휘도펄스를 발생하면 휘도조정회로(2)에서는 이 휘도펄스를 조정하여 제4도의 (b)와 같은 휘도신호를 발생하게 된다.According to the present invention configured as described above, the luminance pulse generating circuit 1 receives the line synchronization signal as an input and generates the luminance pulse as shown in FIG. 4A, and the luminance adjusting circuit 2 adjusts the luminance pulse to the fourth. A luminance signal as shown in (b) of FIG. Is generated.
즉, 휘도조정회로(2)에 입력된 휘도펄스 신호는 비교부(7)를 통하여 저항(R14)(R15)과 볼륨(VR1)(VR2)에 의한 기준전압과 비교된 후 버퍼부(8)를 통하여 제4도의 (b)와 같이 지점(a)에서 지점(b)까지 변화되는 휘도신호를 각 변조회로(3)로 출력하게 된다.That is, the luminance pulse signal input to the luminance adjusting circuit 2 is compared with the reference voltage by the resistors R 14 (R 15 ) and the volume VR 1 (VR 2 ) through the comparator 7 and then buffered. Through the section 8, as shown in FIG. 4 (b), the luminance signal changed from the point a to the point b is outputted to each modulation circuit 3.
따라서, 변조회로(3)에 입력된 R. G. B 신호는 각각 ABL 전압과 휘도신호에 의해 제4도 (d)와 같이 변조된 후 클램프회로(5)로 보내진다.Therefore, the R. G. B signal input to the modulation circuit 3 is modulated as shown in FIG. 4 (d) by the ABL voltage and the luminance signal, respectively, and then sent to the clamp circuit 5.
또한, 이 클램프회로(5)에서는 라인동기 신호에 동기되어 클램프 펄스 발생회로(4)에서 발생되는 클램프 펄스에 의해 제4도 (b)와 같은 휘도신호 부분을 미리 조정된 클램프 레벨조정용 볼륨(VR9) 값에 따라 클램프한다.In the clamp circuit 5, the clamp level adjustment volume VR in which the luminance signal portion as shown in FIG. 4B is adjusted in advance by the clamp pulse generated by the clamp pulse generating circuit 4 in synchronization with the line synchronous signal. 9 ) Clamp according to the value.
이와 같이 클램프된 R. G. B 신호는 CPT 증폭회로(6)에서 각각 광대역 증폭되어 제4도 (c)와 같은 신호로서 각각 R. G. B CPT의 캐소우드에 가해진다.The clamped R. G. B signals are each wideband amplified in the CPT amplification circuit 6 and applied to the cathodes of the R. G. B CPT as signals as shown in FIG.
여기서 제4도 (c)에 나타낸 바와 같이 휘도신호 부분은 라인동기 신호에 동기된 클램프 펄스에 의해 클램프되어 있으므로 휘도조정용 볼륨(VR2)을 조정함에 따라 점선과 같은 클램프 레벨을 중심으로 휘도신호는 지점(e)에서 지점(f) 사이를 이동하게 된다.As shown in FIG. 4 (c), the luminance signal portion is clamped by a clamp pulse synchronized with the line synchronization signal, so that the luminance signal is centered on a clamp level such as a dotted line as the luminance adjustment volume VR 2 is adjusted. It moves from point (e) to point (f).
이상과 같은 본 고안은 동기신호 부분에 휘도펄스를 부가하여 그 펄스에 따라서 직류분 재생을 행하므로써 동기신호 레벨의 휘도에 대한 영향을 완전히 배제할 수 있음은 물론 작동중 직류성분의 변화가 없고 회로의 선형특성이 양호해지는 효과가 있다.As described above, the present invention adds a luminance pulse to the synchronous signal portion and reproduces the DC component according to the pulse, thereby completely eliminating the influence on the luminance of the synchronous signal level, and of course, there is no change in the DC component during operation. This has the effect of improving the linear characteristic of.
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR2019900008810U KR920008996Y1 (en) | 1990-06-21 | 1990-06-21 | Circuit for controlling contrast |
Applications Claiming Priority (1)
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KR2019900008810U KR920008996Y1 (en) | 1990-06-21 | 1990-06-21 | Circuit for controlling contrast |
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KR920001647U KR920001647U (en) | 1992-01-28 |
KR920008996Y1 true KR920008996Y1 (en) | 1992-12-26 |
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KR2019900008810U KR920008996Y1 (en) | 1990-06-21 | 1990-06-21 | Circuit for controlling contrast |
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