KR920008615A - Control Method of Multiple Subprocessors in Multiprocessor System - Google Patents

Control Method of Multiple Subprocessors in Multiprocessor System Download PDF

Info

Publication number
KR920008615A
KR920008615A KR1019900017143A KR900017143A KR920008615A KR 920008615 A KR920008615 A KR 920008615A KR 1019900017143 A KR1019900017143 A KR 1019900017143A KR 900017143 A KR900017143 A KR 900017143A KR 920008615 A KR920008615 A KR 920008615A
Authority
KR
South Korea
Prior art keywords
signal
host processor
subprocessor
data
subprocessors
Prior art date
Application number
KR1019900017143A
Other languages
Korean (ko)
Other versions
KR930005843B1 (en
Inventor
윤성순
이원택
이명원
Original Assignee
박성규
대우통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박성규, 대우통신 주식회사 filed Critical 박성규
Priority to KR1019900017143A priority Critical patent/KR930005843B1/en
Publication of KR920008615A publication Critical patent/KR920008615A/en
Application granted granted Critical
Publication of KR930005843B1 publication Critical patent/KR930005843B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

내용 없음.No content.

Description

다중 프로세서 시스템의 다수의 서브 프로세서 제어방법Control Method of Multiple Subprocessors in Multiprocessor System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 버스 인터페이스를 통하여 호스트 프로세서와 신호 처리부와의 신호 통신을 개략적으로 도시하는 블록도.1 is a block diagram schematically illustrating signal communication between a host processor and a signal processor through a bus interface.

제2도는 제1도의 버스 인터페이스부를 보다 상세히 도시한 것으로, 본 발명에 따른 서브 프로세서 제어방법을 예시하는 도면.FIG. 2 shows the bus interface of FIG. 1 in more detail, illustrating a subprocessor control method in accordance with the present invention. FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 호스트 프로세서 20 : 서브 프로세서10: host processor 20: subprocessor

40 : 제어 신호 발생부 42 : 데이타 방행 제어부40: control signal generator 42: data direction control unit

45 : 인터럽트 집선부45: interrupt concentrator

Claims (2)

하나의 호스트 프로세서와, 상기 호스트 프로세서에 종속하여 자기에게 할당된 데이타를 독립적으로 처리하는 복수의 채널을 갖는 다수의 서브 프로세서를 포함하는 다중 프로세서 시스템의 상기 서브 프로세서 제어방법에 있어서, 상기 호스트 프로세서(10)에 연관된 메모리 수단(12)의 물리적 기억 영역 이외의 가상영역을 상기 서브 프로세서(20)의 각 패널(CH1 내지 CHn)에 제공되어 여러 신호별로 할당하는 단계와 ; 상기 호스트 프로세서(10)로부터 다수의 서브 프로세서(20)로 동일한 신호 또는 데이타가 다운로드될 때, 상기 신호가 할당되어 기억된 상기 메모리 수단(12)내의 해당하는 가상 영역의 어드레스를 지정하여 억세스된 해당 포맷 데이타를 출력하는 단계와 ; 상기 출력된 포맷 데이타를 수신하며, 이 데이타를 버퍼링(buffering)함으로써 상기 서브 프로세서의 각각의 채널에 동일한 데이타를 제공하는 단계를 포함하는 다중 프로세서 시스템의 다수 서브 프로세서 제어방법.In the method of controlling a subprocessor of a multiprocessor system comprising a host processor and a plurality of subprocessors having a plurality of channels that independently process data allocated to the host processor independently of the host processor. A virtual area other than the physical storage area of the memory means 12 associated with 10) is provided to each panel CH1 to CHn of the subprocessor 20 for allocating for each signal; When the same signal or data is downloaded from the host processor 10 to the plurality of subprocessors 20, the corresponding signal is accessed by designating the address of the corresponding virtual area in the memory means 12 in which the signal is allocated and stored. Outputting format data; Receiving the output format data, and buffering the data to provide the same data to each channel of the subprocessor. 제1항에 있어서, 상기 다수의 서브 프로세서(20)에서 처리된 결과를 호스트 프로세서(10)로 일괄 전송할때, 각 서브 프로세서의 각 채널로부터 발생된 인터럽트 요청신호를 접수하여 통합된 한번의 인터럽트 신호를 상기 호스트 프로세서로 출력하는 채널 인터럽트 접선부(45)를 포함하는 다중 프로세서 시스템의 다수 서브 프로세서 제어방법.The integrated interrupt signal of claim 1, wherein when the batched results of the plurality of subprocessors 20 are transmitted to the host processor 10, the interrupt request signal generated from each channel of each subprocessor is received. And a channel interrupt tangential unit (45) for outputting the signal to the host processor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900017143A 1990-10-25 1990-10-25 Method for controlling subprocessor in multiprocessor system KR930005843B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900017143A KR930005843B1 (en) 1990-10-25 1990-10-25 Method for controlling subprocessor in multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900017143A KR930005843B1 (en) 1990-10-25 1990-10-25 Method for controlling subprocessor in multiprocessor system

Publications (2)

Publication Number Publication Date
KR920008615A true KR920008615A (en) 1992-05-28
KR930005843B1 KR930005843B1 (en) 1993-06-25

Family

ID=19305173

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900017143A KR930005843B1 (en) 1990-10-25 1990-10-25 Method for controlling subprocessor in multiprocessor system

Country Status (1)

Country Link
KR (1) KR930005843B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100546780B1 (en) 2003-12-26 2006-01-25 한국전자통신연구원 Voice over packet system using a plurality of digital signal processors and speech processing method therein

Also Published As

Publication number Publication date
KR930005843B1 (en) 1993-06-25

Similar Documents

Publication Publication Date Title
KR910010328A (en) Disk Array Controller With Parity Capability
KR860006743A (en) Data processing systems
EP0061324A3 (en) Computer memory management
KR830010423A (en) Data exchange method of data processing system
KR920008615A (en) Control Method of Multiple Subprocessors in Multiprocessor System
KR950703238A (en) New D2B device address initialisation starts with previous address
KR890007171A (en) Bus master
KR860001379A (en) Microcomputer
JPS63100554A (en) Memory controller
JP2643660B2 (en) Communication control device
KR930004901B1 (en) Memory control unit of computer system by using dynamic ram
KR960703250A (en) PROCESS AND ARRANGEMENT FOR OPERATING A BUS SYSTEM
JPS57105019A (en) Data transfer controlling system
JPH0562786B2 (en)
KR930014113A (en) External storage access method in parallel processing system
JPS5864531A (en) I/o address control system
JPS54148331A (en) Memory control unit
JPS6482148A (en) Memory bank switching device
KR960006403A (en) Transmission device of broadband communication
JPS6341966A (en) Direct memory access transfer device
JPH04241047A (en) Address extension system
KR970071242A (en) Data path control device of a multiprocessing system
KR920009074A (en) N-bit digital pulse generator using personal computer
KR950002517A (en) Time Division Transmission Method of Packet Data
ATE174139T1 (en) BUS ALLOCATION SYSTEM FOR DIGITAL SIGNAL PROCESSORS

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20000407

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee