KR920008615A - Control Method of Multiple Subprocessors in Multiprocessor System - Google Patents
Control Method of Multiple Subprocessors in Multiprocessor System Download PDFInfo
- Publication number
- KR920008615A KR920008615A KR1019900017143A KR900017143A KR920008615A KR 920008615 A KR920008615 A KR 920008615A KR 1019900017143 A KR1019900017143 A KR 1019900017143A KR 900017143 A KR900017143 A KR 900017143A KR 920008615 A KR920008615 A KR 920008615A
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- host processor
- subprocessor
- data
- subprocessors
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
내용 없음.No content.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 버스 인터페이스를 통하여 호스트 프로세서와 신호 처리부와의 신호 통신을 개략적으로 도시하는 블록도.1 is a block diagram schematically illustrating signal communication between a host processor and a signal processor through a bus interface.
제2도는 제1도의 버스 인터페이스부를 보다 상세히 도시한 것으로, 본 발명에 따른 서브 프로세서 제어방법을 예시하는 도면.FIG. 2 shows the bus interface of FIG. 1 in more detail, illustrating a subprocessor control method in accordance with the present invention. FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 호스트 프로세서 20 : 서브 프로세서10: host processor 20: subprocessor
40 : 제어 신호 발생부 42 : 데이타 방행 제어부40: control signal generator 42: data direction control unit
45 : 인터럽트 집선부45: interrupt concentrator
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900017143A KR930005843B1 (en) | 1990-10-25 | 1990-10-25 | Method for controlling subprocessor in multiprocessor system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900017143A KR930005843B1 (en) | 1990-10-25 | 1990-10-25 | Method for controlling subprocessor in multiprocessor system |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920008615A true KR920008615A (en) | 1992-05-28 |
KR930005843B1 KR930005843B1 (en) | 1993-06-25 |
Family
ID=19305173
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900017143A KR930005843B1 (en) | 1990-10-25 | 1990-10-25 | Method for controlling subprocessor in multiprocessor system |
Country Status (1)
Country | Link |
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KR (1) | KR930005843B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100546780B1 (en) | 2003-12-26 | 2006-01-25 | 한국전자통신연구원 | Voice over packet system using a plurality of digital signal processors and speech processing method therein |
-
1990
- 1990-10-25 KR KR1019900017143A patent/KR930005843B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR930005843B1 (en) | 1993-06-25 |
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