KR910021123A - Peak Clip Circuit - Google Patents

Peak Clip Circuit Download PDF

Info

Publication number
KR910021123A
KR910021123A KR1019910007947A KR910007947A KR910021123A KR 910021123 A KR910021123 A KR 910021123A KR 1019910007947 A KR1019910007947 A KR 1019910007947A KR 910007947 A KR910007947 A KR 910007947A KR 910021123 A KR910021123 A KR 910021123A
Authority
KR
South Korea
Prior art keywords
transistor
output
potential difference
circuits
circuit
Prior art date
Application number
KR1019910007947A
Other languages
Korean (ko)
Other versions
KR930006185B1 (en
Inventor
히로야 이토오
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR910021123A publication Critical patent/KR910021123A/en
Application granted granted Critical
Publication of KR930006185B1 publication Critical patent/KR930006185B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/38—Transmitter circuitry for the transmission of television signals according to analogue transmission standards
    • H04N5/40—Modulation circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Picture Signal Circuits (AREA)

Abstract

내용 없음No content

Description

피크·클립회로Peak Clip Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 1실시예에 따른 구성의 회로도.1 is a circuit diagram of a configuration according to an embodiment of the present invention.

제2a도는 제1도의 회로에서의 각 출력의 특성곡선도.2a is a characteristic curve diagram of each output in the circuit of FIG.

제2b도는 제1도의 회로에서의 출력차를 나타낸 특성곡선도.2b is a characteristic curve showing the output difference in the circuit of FIG.

Claims (1)

제1극성의 제1트랜지스터(Q2) 및 제2트랜지스터(Q3)로 구성되고, 제1트랜지스터(Q2)의 베이스단자에 입력신호가 인가되며, 공통에미터가 정상출력으로 되는 차동회로와, 상기 차동회로의 기준전압으로서 입력기준전압에 대해 클립시의 출력잔류전압에 상당하는 오프셋전압을 상기 제2트랜지스터(Q3)의 베이스단자에 인가하는 제1전위차회로(R1, I1) 및, 상기 차동회로의 클립시에 동작하는 상기 제2트랜지스터(Q3)의 콜렉터전류에 비례하는 전위차를 이 제2트랜지스터(Q3)의 베이스단자에 정귀환으로서 인가하는 제2전위차회로(Q4, Q7, R2)를 구비하고서, 상기 제2전위차회로(Q4, Q7, R2)의 전위차변화가 역상출력으로 되어, 상기 정상출력과 역상출력의 차전압출력형으로 한 것을 특징으로 하는 피크·클립회로.A differential circuit comprising a first transistor Q2 and a second transistor Q3 of the first polarity, and having an input signal applied to the base terminal of the first transistor Q2, wherein the common emitter is a normal output; The first potential difference circuits R1 and I1 for applying an offset voltage corresponding to the output residual voltage at the time of the clip to the base terminal of the second transistor Q3 as a reference voltage of the differential circuit, and the differential circuit; Second potential circuits Q4, Q7, and R2 for applying a potential difference proportional to the collector current of the second transistor Q3 operating at the time of the And the potential difference change of the second potential difference circuits (Q4, Q7, R2) is made into a reversed phase output, so that the peak clip circuit is formed as a differential voltage output type of the normal output and the reversed phase output. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910007947A 1990-05-17 1991-05-16 Peak clip circuit KR930006185B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP02-127468 1990-05-17
JP2127468A JP2557552B2 (en) 1990-05-17 1990-05-17 Peak clip circuit
JP?2-127468 1990-05-17

Publications (2)

Publication Number Publication Date
KR910021123A true KR910021123A (en) 1991-12-20
KR930006185B1 KR930006185B1 (en) 1993-07-08

Family

ID=14960677

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910007947A KR930006185B1 (en) 1990-05-17 1991-05-16 Peak clip circuit

Country Status (2)

Country Link
JP (1) JP2557552B2 (en)
KR (1) KR930006185B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007208114A (en) * 2006-02-03 2007-08-16 Disco Abrasive Syst Ltd Cutting device
KR100899259B1 (en) * 2007-05-28 2009-05-26 리믹스포인트, 인코포레이션 Drill inspection apparatus, drill inspection method, and redording media recording the program

Also Published As

Publication number Publication date
JP2557552B2 (en) 1996-11-27
JPH0422206A (en) 1992-01-27
KR930006185B1 (en) 1993-07-08

Similar Documents

Publication Publication Date Title
KR910006732A (en) Current detection circuit
KR870009543A (en) Differential amplifier circuit
KR890001293A (en) Output circuit
KR920020832A (en) Comparator circuit
KR880008518A (en) Filter device
KR910007240A (en) Current mirror circuit
KR910015108A (en) Logarithmic Amplifier Circuit
KR880005744A (en) Differential amplifier
KR880011996A (en) Differential amplifier
KR910007277A (en) Level conversion circuit
KR970024513A (en) Operational amplifier and digital signal transfer circuit
KR950034156A (en) Temperature detection circuit
KR920013863A (en) Power supply with reference circuit and stabilizer circuit
KR910019016A (en) Asymmetric Signal Generation Circuit
KR910021123A (en) Peak Clip Circuit
KR910017735A (en) Amplifier device
KR900004096A (en) Amplification circuit
KR850008253A (en) Differential amplifier
KR930003543A (en) Current mirror circuit
KR880005743A (en) Comparator
KR900012422A (en) Integrated transistor circuit with MOS technology
KR910021007A (en) amplifier
KR850002181A (en) Amplification Circuit of Electric Signal with Electronic Amplification Control
KR910021022A (en) Hysteresis circuit
KR910017743A (en) Level conversion circuit

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030701

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee