KR910015008A - Metal wiring method - Google Patents

Metal wiring method Download PDF

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Publication number
KR910015008A
KR910015008A KR1019900000572A KR900000572A KR910015008A KR 910015008 A KR910015008 A KR 910015008A KR 1019900000572 A KR1019900000572 A KR 1019900000572A KR 900000572 A KR900000572 A KR 900000572A KR 910015008 A KR910015008 A KR 910015008A
Authority
KR
South Korea
Prior art keywords
film
tungsten
forming
metal
metal wiring
Prior art date
Application number
KR1019900000572A
Other languages
Korean (ko)
Other versions
KR930000195B1 (en
Inventor
김의송
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019900000572A priority Critical patent/KR930000195B1/en
Publication of KR910015008A publication Critical patent/KR910015008A/en
Application granted granted Critical
Publication of KR930000195B1 publication Critical patent/KR930000195B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음No content

Description

금속배선방법Metal wiring method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도 (Å) 내지 (C)는 본 발명의 개선된 블랭킷 텅스텐막의 제조공정도.1 (i) to (C) are process drawings of the improved blanket tungsten film of the present invention.

Claims (3)

실리콘 기판(1)에 접촉영역(2), 절연막(3)을 형성한 후, 배선용으로 텅스텐막을 형성하는 반도체 장치의 제조방법에 있어서, 상기 실리콘 기판(1)상에 텅스텐막의 부착력을 향상시키기 위한 금속막(4)을 형성하는 제1공정과, 상기 금속막(4)상에 거칠기가 나빠지지 않는 정도의 얇은 두께로 텅스텐막(5)을 1차로 형성시키는 제2공정과, 상기 텅스텐막(5)상에 텅스텐막의 거칠기를 억제하기 위한 텅스텐 실리사이드 (6)를 형성하는 제3공정과, 상기 텅스텐 실리사이드막(6)상에 텅스텐막을 2차로 형성시키는 제4공정과, 상기 제3 내지 제5공정을 연속적으로 반복하여 원하는 두께로 텅스텐막을 형성하는 것을 특징으로 하는 금속배선 형성방법.In the method of manufacturing a semiconductor device in which a contact region 2 and an insulating film 3 are formed on a silicon substrate 1, and a tungsten film is formed for wiring, the method for improving the adhesion of the tungsten film on the silicon substrate 1 is provided. A first step of forming the metal film 4, a second step of forming the tungsten film 5 first in a thin thickness such that the roughness does not deteriorate on the metal film 4, and the tungsten film ( 5) a third step of forming a tungsten silicide 6 for suppressing the roughness of the tungsten film, a fourth step of forming a tungsten film secondary on the tungsten silicide film 6, and the third to fifth steps. Forming a tungsten film with a desired thickness by successively repeating the process. 상기 제1항에 있어서, 2차로 텅스텐막(5)의 형성하기 위한 제5공정시, 텅스텐 실리사이드막(6)이 WF6개스와 반응하여 텅스텐으로 환원되어지는 것을 특징으로 하는 금속배선방법.2. The metal wiring method according to claim 1, wherein in the fifth process for forming the tungsten film (5) in the second step, the tungsten silicide film (6) is reduced to tungsten by reacting with WF6 gas. 제1항에 있어서, 금속막(4)으로 티타늄막을 300Å으로 형성한 후 2차로 질화티타늄막을 900Å으로 스퍼터링 방법을 이용하여 형성하는 것을 특징으로 하는 금속배선방법.2. The metal wiring method according to claim 1, wherein a titanium film is formed of 300 mW using the metal film (4), and then a titanium nitride film is formed at 900 mW using a sputtering method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900000572A 1990-01-18 1990-01-18 Metal wiring method of semiconductor device KR930000195B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900000572A KR930000195B1 (en) 1990-01-18 1990-01-18 Metal wiring method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900000572A KR930000195B1 (en) 1990-01-18 1990-01-18 Metal wiring method of semiconductor device

Publications (2)

Publication Number Publication Date
KR910015008A true KR910015008A (en) 1991-08-31
KR930000195B1 KR930000195B1 (en) 1993-01-11

Family

ID=19295371

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900000572A KR930000195B1 (en) 1990-01-18 1990-01-18 Metal wiring method of semiconductor device

Country Status (1)

Country Link
KR (1) KR930000195B1 (en)

Also Published As

Publication number Publication date
KR930000195B1 (en) 1993-01-11

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