KR910013885A - Interpolation Circuit in Television Receiver - Google Patents

Interpolation Circuit in Television Receiver Download PDF

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Publication number
KR910013885A
KR910013885A KR1019890019921A KR890019921A KR910013885A KR 910013885 A KR910013885 A KR 910013885A KR 1019890019921 A KR1019890019921 A KR 1019890019921A KR 890019921 A KR890019921 A KR 890019921A KR 910013885 A KR910013885 A KR 910013885A
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KR
South Korea
Prior art keywords
output
line memory
line
memory
units
Prior art date
Application number
KR1019890019921A
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Korean (ko)
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KR920003089B1 (en
Inventor
이명환
Original Assignee
강진구
삼성전자 주식회사
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Publication date
Application filed by 강진구, 삼성전자 주식회사 filed Critical 강진구
Priority to KR1019890019921A priority Critical patent/KR920003089B1/en
Publication of KR910013885A publication Critical patent/KR910013885A/en
Application granted granted Critical
Publication of KR920003089B1 publication Critical patent/KR920003089B1/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/30Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical otherwise than with constant velocity or otherwise than in pattern formed by unidirectional, straight, substantially horizontal or vertical lines

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)
  • Color Television Systems (AREA)

Abstract

내용 없음.No content.

Description

텔레비젼 수상기에 있어서 인터폴레이션 회로Interpolation Circuit in Television Receiver

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도는 본 발명에 따른 회로도,5 is a circuit diagram according to the present invention,

제6도는 본 발명에 따른 정지화 주사선 보간도,6 is a still picture scanning line interpolation diagram according to the present invention,

제7도는 본 발명에 따른 동화 처리도.7 shows an assimilation process according to the present invention.

Claims (1)

Y성분 콤필터(3)와, 움직임 검출회로(2)를 구비한 TV의 인터플레이션 회로에 있어서, 상기 Y성분 콤필터(3)의 출력단(31)의 출력을 주사선 라인단위로 저항하는 제1라인메모리(51)와, 상기 출력단(31)의 출력과 상기 제1라인메모리 (51)의 출력을 가산하는 가산기(591)와, 상기 제1라인메모리(51) 의 출력을 주사선 라인단위로 저장하는 제2라인메모리(54) 와, 상기 가산기(591)의 출력을 라인단위로 저장하는 제4라인메모리(52)와, 상기 제1라인메모리(53)의 출력을 화면의 필드단위로 저장하는 필드메모리(53)와, 상기 필드메모리(53)의 출력데이타를 주사선 라인단위로 저장하는 제3라인메모리(55)와, 상기 제1,2.3라인메모리(51,54,55) 및 필드메모리(53) 와 상기 출력단(31)의 입력을 에지검출단(592)을 통해 입력되는 신호에 보간하여 정지화상의 보간신호로 출력하는 정지화 화상보간 연산기(56)와, 상기 제1라인메모리(51) 및 가산기(591)의 출력과 제4라인메모리(52)의 출력을 보간하여 동화상보간신호로 출력하는 동화상보간연산기(57)와, 상기 움직임 검출회로(2)의 발생 움직임 검출신호단(4)의 입력에 따라 상기 정지/동화상 보간연산기(56,57)의 출력을 처리하여 움직임 신호를 발생하는 움직임 처리회로(58)와, 상기 움직임 처리회로(58)의 출력을 3배의 수평주파수로 스위칭하여 3배의 주사선을 가지도록 선택 출력하는 스위치(59)로 구성함을 특징으로 하는 회로.A television interpolation circuit having a Y component comb filter (3) and a motion detection circuit (2), comprising: a first resistor for resisting the output of the output terminal (31) of the Y component comb filter (3) in units of scan lines; A line memory 51, an adder 591 for adding an output of the output terminal 31 and an output of the first line memory 51, and an output of the first line memory 51 in units of scan lines A second line memory 54, a fourth line memory 52 for storing the output of the adder 591 in line units, and an output of the first line memory 53 in field units of a screen. A field memory 53, a third line memory 55 for storing output data of the field memory 53 in units of scan lines, the first, 2.3 line memories 51, 54, 55 and a field memory ( 53) and a still image which interpolates the input of the output terminal 31 to the signal input through the edge detection terminal 592 and outputs the interpolated signal of the still image. A video interpolation calculator 57, a video interpolation calculator 57 for interpolating the outputs of the first line memory 51 and the adder 591 and the outputs of the fourth line memory 52 and outputting them as a video interpolation signal; A motion processing circuit 58 for generating a motion signal by processing the outputs of the still / video interpolation operators 56 and 57 according to the input of the motion detection signal stage 4 generated by the motion detection circuit 2; And a switch (59) for selectively outputting the output of the motion processing circuit (58) at three times the horizontal frequency to have three times the scan line. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890019921A 1989-12-28 1989-12-28 Interpolation circuit in tv KR920003089B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890019921A KR920003089B1 (en) 1989-12-28 1989-12-28 Interpolation circuit in tv

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890019921A KR920003089B1 (en) 1989-12-28 1989-12-28 Interpolation circuit in tv

Publications (2)

Publication Number Publication Date
KR910013885A true KR910013885A (en) 1991-08-08
KR920003089B1 KR920003089B1 (en) 1992-04-13

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ID=19293985

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890019921A KR920003089B1 (en) 1989-12-28 1989-12-28 Interpolation circuit in tv

Country Status (1)

Country Link
KR (1) KR920003089B1 (en)

Also Published As

Publication number Publication date
KR920003089B1 (en) 1992-04-13

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