KR910013718A - Port Switching Control in Redundant Systems - Google Patents

Port Switching Control in Redundant Systems Download PDF

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Publication number
KR910013718A
KR910013718A KR1019890020552A KR890020552A KR910013718A KR 910013718 A KR910013718 A KR 910013718A KR 1019890020552 A KR1019890020552 A KR 1019890020552A KR 890020552 A KR890020552 A KR 890020552A KR 910013718 A KR910013718 A KR 910013718A
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KR
South Korea
Prior art keywords
signal
state buffer
redundant
output
output signal
Prior art date
Application number
KR1019890020552A
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Korean (ko)
Other versions
KR920007261B1 (en
Inventor
최영복
여환근
송형선
Original Assignee
경상현
재단법인 한국전자통신연구소
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Priority to KR1019890020552A priority Critical patent/KR920007261B1/en
Publication of KR910013718A publication Critical patent/KR910013718A/en
Application granted granted Critical
Publication of KR920007261B1 publication Critical patent/KR920007261B1/en

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking

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  • Hardware Redundancy (AREA)
  • Safety Devices In Control Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

내용 없음.No content.

Description

이중화된 시스템의 포트 스위칭 제어장치Port Switching Control in Redundant Systems

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명이 적용되는 이중화 시스템 구성도,1 is a configuration diagram of a redundant system to which the present invention is applied;

제2도는 본 발명의 전체 구성도.2 is an overall configuration diagram of the present invention.

Claims (2)

전전자 교환기의 맨-머신 인터페이스(man-machine interface)를 위한 이중화된 프로세서 시스템에 있어서, 이중화된 서브시스템(1,2)의 이중화 제어신호를 입력으로 받아 동작상태인 어느하나의 서브시스템이 장애발생으로 인하여 대기 상태로 변환할 때 이중화 제어신호가 동작상태 신호로 계속 유지됨으로 발생하는 오동작을 방지하는 이중화 제어수단(10), 상기 이중화 제어수단(10)에 연결되어 서브시스템(1,2)의 출력신호와 이중화 제어수단(10)의 출력신호를 입력으로 받아 정상동작 상태인 서브시스팀의 출력신호만 전송하는 출력신호 MUX수단(20), 상기 출력신호 MUX수단(20)에 연결되어 신호전달 대상장치(4)로 출력되는 출력신호를 구동하고 신호전달 대상장치(4)로 부터의 입력신호를 상기 이중화된 서브시스템(1,2)으로 직접 구동하는 신호 구동수단(30)으로 구성된 것을 특징으로 하는 이중화 시스템의 포트 스위칭 제어장치.In a redundant processor system for a man-machine interface of an electronic switching system, any one subsystem operating in response to a redundant control signal of the redundant subsystem (1, 2) is interrupted. The redundancy control means 10, which is connected to the redundancy control means 10, which prevents a malfunction caused by the redundancy control signal being kept as an operation state signal when switching to the standby state due to the occurrence, is connected to the subsystems 1 and 2 Connected to the output signal MUX means 20 and the output signal MUX means 20 for receiving only the output signal of the control unit and the output signal of the redundancy control means 10 and transmitting only the output signal of the subsystem in a normal operation state. To signal drive means 30 for driving an output signal output to the target device 4 and directly driving the input signal from the signal transfer target device 4 to the redundant subsystems 1 and 2; Port switching control device of the redundant system, characterized in that configured. 제1항에 있어서, 상기 이중화 제어수단(10)은 이중화된 양측 서브시스템(1,2)의 동작/대기 상태신호를 입력으로 받는 제1 3-상태버퍼(11)와 제2 3-상태버퍼(12), 상기 제1 3-상태버퍼(11)와 제2 3-상태 버퍼(12)의 출력단에 두 입력단자가 연결된 NOR게이트(13), 상기 NOR게이트(13)의 출력단에 클럭단자가, 상기 제1 3-상태버퍼(11)와 제2 3-상태버퍼(12)의 제어단자에 Q출력단자가 각각 연결된 제1 D플립플롭(14)과 제2 D플립플롭(15), 상기 제1 3-상태버퍼(11)와 제2 3-상태 버퍼(12)의 출력단에 두 입력단자가 연결된 ENOR게이트(16)로 구성된 것을 특징으로 하는 이중화 시스템의 포트 스위칭 제어장치.The first three-state buffer (11) and the second three-state buffer of claim 1, wherein the redundancy control means (10) receives as inputs operation / standby status signals of both redundant subsystems (1,2). (12), a NOR gate 13 having two input terminals connected to the output terminals of the first three-state buffer 11 and the second three-state buffer 12, and a clock terminal at the output terminal of the NOR gate 13; A first D flip-flop 14 and a second D flip-flop 15 connected to a control terminal of the first three-state buffer 11 and the second three-state buffer 12, respectively; A port switching control device of a redundancy system, comprising an ENOR gate (16) connected to two input terminals at an output of a three-state buffer (11) and a second three-state buffer (12). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890020552A 1989-12-30 1989-12-30 Photo switching controller for doubled system KR920007261B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890020552A KR920007261B1 (en) 1989-12-30 1989-12-30 Photo switching controller for doubled system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020552A KR920007261B1 (en) 1989-12-30 1989-12-30 Photo switching controller for doubled system

Publications (2)

Publication Number Publication Date
KR910013718A true KR910013718A (en) 1991-08-08
KR920007261B1 KR920007261B1 (en) 1992-08-28

Family

ID=19294594

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890020552A KR920007261B1 (en) 1989-12-30 1989-12-30 Photo switching controller for doubled system

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KR (1) KR920007261B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100286539B1 (en) * 1998-04-16 2001-04-16 박종섭 Method for managing of duplicate no.7 processor in mobile communication exchange
KR100422144B1 (en) * 1999-10-29 2004-03-10 엘지전자 주식회사 Apparatus for dual controlling of communication port in electronic switching system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100286539B1 (en) * 1998-04-16 2001-04-16 박종섭 Method for managing of duplicate no.7 processor in mobile communication exchange
KR100422144B1 (en) * 1999-10-29 2004-03-10 엘지전자 주식회사 Apparatus for dual controlling of communication port in electronic switching system

Also Published As

Publication number Publication date
KR920007261B1 (en) 1992-08-28

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