KR910007197Y1 - Brightness correction circuit - Google Patents
Brightness correction circuit Download PDFInfo
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- KR910007197Y1 KR910007197Y1 KR2019880017185U KR880017185U KR910007197Y1 KR 910007197 Y1 KR910007197 Y1 KR 910007197Y1 KR 2019880017185 U KR2019880017185 U KR 2019880017185U KR 880017185 U KR880017185 U KR 880017185U KR 910007197 Y1 KR910007197 Y1 KR 910007197Y1
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- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
- G09G1/002—Intensity circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
- G09G1/04—Deflection circuits ; Constructional details not otherwise provided for
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
- G09G1/28—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using colour tubes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
내용 없음.No content.
Description
제1도는 본 고안을 설명하기 위하 도면으로서 라스터를 디스플레이 시킬때 휘도가 스크린의 중앙부 보다 주면부에서 저하됨을 예시한 도면.FIG. 1 is a view for explaining the present invention, which illustrates that the luminance is lowered at the main surface than the center of the screen when the raster is displayed.
제2도는 본 고안에 따른 휘도 보정회로의 블럭도.2 is a block diagram of a luminance correction circuit according to the present invention.
제3도는 본 고안에 따른 상세 회로도.3 is a detailed circuit diagram according to the present invention.
제4도는 제3도의 주요부분에 있어서의 출력신호 파형도이다.4 is an output signal waveform diagram in the main part of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 수직신호입력단자 20 : 수평신호입력단자10: vertical signal input terminal 20: horizontal signal input terminal
30 : 파볼라신호발생부 40 : 증폭부30: pabola signal generator 40: amplification unit
50 : 브라운관50: CRT
본 고안은 브라운관의 휘도보정 회로에 관한 것으로서, 상세하게는 제1그리드 전압을 보정하여 칼라브라운관의 전체화면에서 동일한 휘도를 갖게하는 휘도보정 회로에 관한 것이다.The present invention relates to a luminance correction circuit of a CRT, and more particularly, to a luminance correction circuit for correcting a first grid voltage to have the same luminance in the entire screen of a color CRT.
칼라브라운관이 고정세화되고, 이러한 브라운관의 화면이 대형화됨에 따라 브라운관 화면의 중앙부와 주면부간에 생기는 색순도차를 제거하기 위한 목적으로 화면의 중앙부에서 주변부로 갈수록 R.G.B 형광체 사이에 있는 블랙 매트릭스(black matrix)부분이 점차 넓어지는 구조로 되어 있다.As the color CRT becomes high definition and the CRT screen becomes larger, a black matrix between RGB phosphors from the center to the periphery of the screen for the purpose of eliminating the color purity difference between the center and the main surface of the CRT screen. The structure is gradually widened.
따라서, 칼라브라운관의 캐소우드(Cathode)에 영상신호를 공급하여 칼라브라운관을 구동하는 경우, 영상신호의 이득은 수평편향신호와 수직편향신호의 임의 주기내에서 변동없이 일정한 값을 갖고 있기 때문에 상기에서 언급한 화면구조를 갖는 칼라 브라운관의 화면전역에 동일한 비임(beem)전류로 백색의 라스터(raster)를 표시할때 화면주변부의 휘도는 화면 중앙부의 휘도에 비해 저하된다.Therefore, when driving a color brown tube by supplying a video signal to the cathode of the color brown tube, the gain of the video signal has a constant value without any change within an arbitrary period of the horizontal deflection signal and the vertical deflection signal. When displaying a white raster with the same beam current in the entire screen of a color CRT having the screen structure mentioned above, the brightness of the periphery of the screen is lower than that of the center of the screen.
이와 같이, 칼라브라운관 화면의 주변부가 제1도가 예시한 바와 같이 중앙부 보다 휘도가 저하됨에 따라 주변부가 어두워져서, 화면일부가 얼룩져 보이는 현상이 나타나 화질이 떨어지는 결점이 있었다.As described above, as shown in FIG. 1, the peripheral portion of the color CRT screen becomes darker than the central portion, and thus the peripheral portion becomes darker, and thus a portion of the screen appears stained, resulting in a poor image quality.
본 고안은 칼라브라운관의 구동에 있어 칼라브라운관 화면의 중앙부를 기준하여 수직방향과 수평방향의 주변부로 갈수록 화면의 휘도가 점차 저하되는 현상을 해결하여 브라운관의 전제화면의 휘도분포가 균일하게 하는 휘도 보정회로를 제공하는데 그 목적이 있다.The present invention solves the phenomenon that the brightness of the screen gradually decreases toward the periphery of the vertical and horizontal directions with respect to the center of the screen of the color CRT in the operation of the color CRT. The purpose is to provide a circuit.
상기한 목적을 달성하기 위한 수단으로서, 본 고안은 브라운관의 제1그리드에 제공되는 그리드전압을 수평편향신호와 수직편향신호의 주기에 따라 보상하여 수평, 수직주기의 시작부분은, 예컨대 화면의 좌축 및 상측의 주변부는 그리드 보정전압을 크게하고 아울러 중앙부에서는 그리드 보정전압은 낮게하며, 다시 수평, 수직주기의 마지막 부분, 예컨대 화면 우측 및 하측의 주변부에서는 그리드 보정전압을 크게하는 휘도 보정회로를 특징으로 하는 바, 이를 첨부도면에 따른 본 고안의 실시예를 통해 구체적으로 설명한다.As a means for achieving the above object, the present invention compensates the grid voltage provided to the first grid of the CRT according to the period of the horizontal deflection signal and the vertical deflection signal so that the beginning of the horizontal and vertical periods is, for example, the left axis of the screen. And a luminance correction circuit that increases the grid correction voltage at the upper periphery and lowers the grid correction voltage at the center, and increases the grid correction voltage at the last part of the horizontal and vertical periods, for example, at the right and lower periphery of the screen. It will be described in detail through an embodiment of the present invention according to the accompanying drawings.
제2도는 본 고안에 따른 휘도 보정회로의 블럭도로서, 수상기의 영상검파기(도면에 도시되어 있지 않음)에서 출력되는 칼러 합성 영상신호(명도신호, 색도신호, 동기신호 및 칼러버어스트 신호를 포함하고 있음)를 필요한 크기까지 증폭하고, 동기회로나 대역증폭회로에 신호분배를 하며, 또한 색신호와 휘도신호의 대역폭의 차이에 의한 지연시간의 보정과 직류분의 재생 및 고역특성의 보상을 하는 영상증폭회로(도면에 도시되어 있지 않음)에서 제공되는 영상신호가 브라운관 드라이버 및 영상출력부를 통해 브라운관(50)의 캐소오드로 제공되게 하고, 단자(10)(20)를 각각 통해 인가되는 수직신호와 수평신호는 파라볼라신호발생부(30)를 거쳐 하나의 파라볼라신호로 합성된 다음 증폭부(40)에서 증폭되어 브라운관(50)의 제1그리드단자로 제공되도록 한 회로이다.2 is a block diagram of a luminance correction circuit according to the present invention, and the color composite image signal (brightness signal, chromaticity signal, synchronization signal and color burst signal) output from an image detector (not shown) of the receiver is shown. Amplified to the required size, signal distribution to the synchronous circuit or the bandwidth amplifier circuit, and correction of the delay time by the difference of the bandwidth of the color signal and the luminance signal, the reproduction of the DC component, and the compensation of the high frequency characteristic. The video signal provided from the amplifying circuit (not shown) is provided to the cathode of the CRT 50 through the CRT driver and the image output unit, and the vertical signal applied through the terminals 10 and 20 respectively. The horizontal signal is synthesized into one parabola signal via the parabola signal generator 30 and then amplified by the amplification unit 40 to be provided to the first grid terminal of the CRT 50. Circuit.
상기의 수직신호 입력단자(10)와 수평신호 입력단자(20)는 각각 통상적인 브라운관의 수평편향회로와 수평편향회로에서 제공되는 신호들을 출력하는 단자와 접속된다.The vertical signal input terminal 10 and the horizontal signal input terminal 20 are connected to terminals for outputting signals provided from a horizontal deflection circuit and a horizontal deflection circuit of a conventional CRT, respectively.
이러한 구성을 갖는 본 고안의 상세회로도는 제3도에 도시되어 있다.A detailed circuit diagram of the present invention having such a configuration is shown in FIG.
단자(10)를 통해 입력되는 수직 편향 주기에 상응하는 수직신호는 수직편향 코일 L1을 거친다음 블로킹 다이오드D1를 통해 증폭부(40)로 제공되고, 단자(20)를 통해 입력되는 수평 편향주기에 상응하는 수평신호는 수평편향 코일 L2를 거친다음 저항R2, 블로킹 다이오드D2를 통해 상기의 증폭부(40)로 제공된다.The vertical signal corresponding to the vertical deflection period input through the terminal 10 passes through the vertical deflection coil L 1 and then is provided to the amplifier 40 through the blocking diode D 1 , and the horizontal deflection input through the terminal 20. The horizontal signal corresponding to the period passes through the horizontal deflection coil L 2 and then is provided to the amplifier 40 through the resistor R 2 and the blocking diode D 2 .
상기 수직편향 코일 L1과 다이오드 D1의 접속단에 직렬 연결된 콘덴서 C1와 접지된 저항 R1이 연결되어 있어 수직신호가 제4도(a)와 같은 파라볼라(parabola)파형으로 변환되고, 수평편향 코일 L2과 저항 R2사이의 접속점에는 접지된 콘덴서 C2과 연결되어 있어 수평신호가 제4도(b)와 같은 파라볼라 파형으로 변환되는 바, 이러한 수직 또는 수평편향의 파라볼라 신호는 편향 주기와 일치한다.The capacitor C 1 connected in series to the connection terminal of the vertical deflection coil L 1 and the diode D 1 is connected to a grounded resistor R 1 so that the vertical signal is converted into a parabola waveform as shown in FIG. The connection point between the deflection coil L 2 and the resistor R 2 is connected to the grounded capacitor C 2 so that the horizontal signal is converted into a parabolic waveform as shown in FIG. 4 (b). Matches
따라서, 파라볼라 신호 발생부(30)의 출력단에서는 수직, 수평편향의 두 파라볼라 신호를 제4도(c)의 파형과 같이 합성하여 증폭부(40)제공되게 한다.Therefore, at the output of the parabola signal generator 30, two parabola signals of vertical and horizontal deflection are synthesized as shown in the waveform of FIG.
합성된 파라볼라 신호는 콘덴서C3, 바이어스저항R5을 거쳐 증폭용 트랜지스터 Q1의 베이스에 제공되고, 이 트랜지스터Q1의 콜렉터에는 상기신호의 반전되어 나타나서 2차 증폭용 트랜지스터Q2의 베이스에 제공되며, 트랜지스터Q2의 콜렉터에는 다시 파라볼라신호와 위상이 같은 증폭신호가 출력되어서 콘덴서C4를 통해 브라운관(50)의 제1그리드로 제공된다.The synthesized parabola signal is provided to the base of the amplifying transistor Q 1 via a capacitor C 3 and a bias resistor R 5 , and the collector of this transistor Q 1 appears inverted and provided to the base of the second amplifying transistor Q 2 . The amplification signal having the same phase as that of the parabola signal is again output to the collector of the transistor Q 2 , and is provided to the first grid of the CRT 50 through the capacitor C 4 .
저항 R6-R9은 바이어스 저항이고, 저항 R3과 R4는 분압저항으로 이용된다.Resistors R 6 -R 9 are bias resistors, and resistors R 3 and R 4 are used as voltage divider resistors.
즉, 합성 파라볼라신호가 트랜지스터Q1의 베이스에 인가됨에 따라 트랜지스터Q2의 콜렉터-에미터 바이어스전압이 변화되고 아울러 트랜지스터Q2의 베이스에 인가되는 합성 파라볼라신호가 증폭되어 트랜지스터Q3의 콜렉터에서 출력되는바, 이 신호(제4도의 c)는 제1그리드에 제공되는 전압VG1과 함께 제1그리드에 제공된다.That is, the composite parabolic signal is the collector of transistor Q 2 as applied to the transistor Q 1 base-emitter bias voltage is changed as well is a synthetic parabolic signal applied to the transistor Q 2 base amplified output from the transistor Q 3 Collector This signal (c in FIG. 4) is provided to the first grid along with the voltage V G1 provided to the first grid.
증폭된 합성 파라볼라 신호가 수직, 수평 편향신호의 임의 주기내에서 변동없이 일정한 값을 갖게하는 것이 아니라 수직, 수평편향신호의 주기에 따라 그리드 전압이 보정되도록 하여, 수평 또는 수직주기의 시작 및 마지막 부분인 주변부에서는 크게 보상하고, 중앙부분인 수평 또는 수직주기의 가운데에서는 낮게 보상하도록한 것이다.The amplified synthesized parabola signal does not have a constant value without fluctuation within any period of the vertical and horizontal deflection signals, but the grid voltage is corrected according to the period of the vertical and horizontal deflection signals, so that the beginning and the end of the horizontal or vertical period are In the periphery of phosphorus, the compensation is large, and in the middle of the horizontal or vertical period, which is the central part, the compensation is low.
즉, 상기한 제1그리드전압VG1이 낮은 쪽에서는 높은 전압의 합성파라볼라신호를 제공하여 휘도를 높히고, VG1이 높은 쪽에서는 낮은 전압의 합성 파라볼라신호를 제공하여 휘도를 낮추어서 브라운관(50)의 전체화면에서 동일한 휘도를 갖게한다.That is, the one of the first grid voltage V G1 is a low-side, nophigo the brightness by providing a composite parabolic signal of a high voltage side of a high V G1 is lowered the brightness by providing a composite parabolic signal in the low voltage cathode-ray tube (50) Have the same brightness across the entire screen.
이상에서 설명한 바와 같이 본 고안에 의하면, 브라운관의 화면전체에 동일한 휘도를 갖도록 하여 주변부에서의 휘도차에 의해 생기는 얼룩현상이 제거되므로써 화질을 개선시킬 수 있다.As described above, according to the present invention, the image quality can be improved by removing the unevenness caused by the luminance difference in the peripheral part by making the entire screen of the CRT the same luminance.
Claims (1)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019880017185U KR910007197Y1 (en) | 1988-10-24 | 1988-10-24 | Brightness correction circuit |
| JP1270135A JPH03205966A (en) | 1988-10-18 | 1989-10-17 | Brightness correction circuit |
| DE19893934762 DE3934762A1 (en) | 1988-10-18 | 1989-10-18 | CRT brightness control circuit - uses combined parabolic signals obtained from horizontal and vertical deflection signals |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019880017185U KR910007197Y1 (en) | 1988-10-24 | 1988-10-24 | Brightness correction circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR900009337U KR900009337U (en) | 1990-05-04 |
| KR910007197Y1 true KR910007197Y1 (en) | 1991-09-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019880017185U KR910007197Y1 (en) | 1988-10-18 | 1988-10-24 | Brightness correction circuit |
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| Country | Link |
|---|---|
| KR (1) | KR910007197Y1 (en) |
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1988
- 1988-10-24 KR KR2019880017185U patent/KR910007197Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR900009337U (en) | 1990-05-04 |
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