KR910005700B1 - Wire phase detector of super high earth wire - Google Patents

Wire phase detector of super high earth wire Download PDF

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KR910005700B1
KR910005700B1 KR1019880010477A KR880010477A KR910005700B1 KR 910005700 B1 KR910005700 B1 KR 910005700B1 KR 1019880010477 A KR1019880010477 A KR 1019880010477A KR 880010477 A KR880010477 A KR 880010477A KR 910005700 B1 KR910005700 B1 KR 910005700B1
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phase
integrated circuit
semiconductor integrated
voltage
point
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KR900003637A (en
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오상은
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오상은
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
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Abstract

This instrument offers a capability of discriminating In- phase or Out-of- phase by sensing voltage induced on the basic insulating plug (BIP) as detecting terminal and outdoor transformer voltage test point, and comparing phase differences in 22.9 kv-y underground distribution networks. This gives good handling which can measure directly phase voltage without power line off and enhance reliability in supplying power, security and time-loss due to the work. the system is composed of two measuring point A, B level moving circuits, AC signal to square wave converter, input signal discriminator of each point, phase comparator and logic comparator. The remainings are for displaying results, i.e. one line disconnection, In-phase and out-of-phase.

Description

특고압 지중 배전 선로용 상판별기Top Separator for Special High Voltage Underground Power Distribution Line

제1도는 본 발명의 회로도.1 is a circuit diagram of the present invention.

제2도는 본 발명의 블럭도.2 is a block diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : U1, U2, U3, U4: 반도체 직접회로 2 : R1, R2, R5-R18: 저항1: U 1 , U 2 , U 3 , U 4 : Semiconductor Integrated Circuit 2: R 1 , R 2 , R 5 -R 18 : Resistance

3 : R3, R4: 가변저항기 4 : C1-C6: 콘덴서.3: R 3 , R 4 : Variable resistor 4: C 1 -C 6 : Condenser.

본 발명은 특고압 지중 배전 선로용 상판별기에 관한 것으로써, 특고압 지중 배전 선로 개폐장치의 검전확인 단자인 BIP(BASIC INSULATIONG PLUG)의 발생 유기전압을 이용하여 22.9KV-Y 배전 교류선로상측정을 할 수 있도록 한 것으로 좀더 상세하게 설명하면, 지중 개폐장치 검전확인 단자의 유기전압의 AC 입력신호 유무와 두 입력신호의 위상차를 동시에 비교 검출하여 상판별을 할 수 있도록 하는데 그 목적이 있다.The present invention relates to an upper discriminator for an extra-high voltage underground distribution line, and measures a 22.9 KV-Y distribution ac line by using a generated induced voltage of a BIP (BASIC INSULATIONG PLUG) terminal, which is a test confirmation terminal of the switch unit for an extra-high voltage underground distribution line. As described in more detail, the purpose of the present invention is to compare and detect the presence or absence of the induced voltage of the induced voltage of the ground switching device inspection confirmation terminal and the phase difference between the two input signals at the same time.

종래 사용하고 있는 상측정기는 가공선로용으로서 지중 배전 선로에는 사용이 불가능하며 또한, 지중 배전 선로와 같이 충전부위가 노출되어 있지 않은 선로의 상측정은 현재로서는 불가능한 실정에 있으며 또한 지중 선로의 상측정은 활선(전기 살아 있는)상태에서 측정이 불가하여 전기를 정전시킨후 변전소의 모선으로 부터 전화통화 방식을 이용함으로써 측정의 정확성을 기할 수 없으며, 많은 인력과 신간이 소요되며 전기공급 신뢰도에 많은 문제점이 있었다.Conventional phase measuring instruments are not available for underground distribution lines as overhead lines, and phase measurement of lines that do not have exposed parts such as underground distribution lines is currently impossible. The measurement is impossible in the live (electric live) state, and it is impossible to measure the accuracy of the measurement by using the telephone call method from the substation's bus after the power failure. There was this.

본 발명은 이와같은 문제점을 해결하기 위하여 발명된 것으로 첨부된 회로도에 의해 상세하게 설명하면 다음과 같다.The present invention is described in detail by the accompanying circuit diagram as invented to solve such a problem as follows.

제1도는 본 발명의 회로도로서, 도면중 U1-U4는 반도체 직접회로(TTLIC), R1, R2, R5-R18은 저항, R3-R4는 가변저항기, C1-C6는 콘덴서이며, A 단자와 반도체 직접회로(U1)의 핀 1, 핀 2 사이에 저항 R1, 가변저항R3, 콘덴서 C1, 저항 R5, R6, 다이오드 D1,D2를 연결하고 반도체 직접회로(U1)의 핀 3을 반도체 직접회로 U2, U3의 핀 11과 핀 1에 연결하며, 반도체 직접회로 U2의 핀 12, 15, 14에 콘덴서 C3, 저항 R10, 다이오드 D5가 연결되며, 동 회로(U2)의 핀 10을 반도체 직접회로(U3)(U4)의 핀 8과 핀 1에 연결하고, 동 회로(U3)의 핀 10은 저항 R12, R15, 트렌지스터 Q1, 다이오드 D7를 구성된 한쪽선 열불량 램프구동회로와 연결하였다. 또 B 단자와 반도체 직접회로(U1)의 핀 5, 핀6 사이에 저항 R2, 가변저항 R4, 콘덴서 C2, 저항 R7, R8, 다이오드 D3, D4를 연결하고, 반도체 직접회로(U1)의 핀 4를 반도체 직접회로 U2, U3의 핀 5와 핀 2에 연결하며, 반도체 직접회로 U2의 핀 4,1,2에 콘덴서 C4, 저항 R11, 다이오드 D6가 연결되며, 동 회로(U2)의 핀 6은 반도체 직접회로(U3)(U4)의 핀 9와 핀 2에 연결하고, 반도체 직접회로(U4)의 핀 3과 반도체 직접회로 U4의 핀 5 와 핀 8에 연결하고 동 회로(U4)의 핀 4는 저항 R13, R16, 트랜지스터 Q2, 다이오드 D8로 구성되는 위상같음 램프구동회로와 연결하였다.1 is a circuit diagram of the present invention, in which U 1 -U 4 is a semiconductor integrated circuit (TTLIC), R 1 , R 2 , R 5 -R 18 is a resistor, R3-R4 is a variable resistor, C 1 -C 6 Is a capacitor and connects resistor R 1 , variable resistor R 3 , capacitor C 1 , resistor R 5 , R 6 , diode D 1 , D 2 between terminal A and pin 1 and pin 2 of semiconductor integrated circuit (U 1 ). and the pin 3 of the semiconductor integrated circuits (U 1) a semiconductor integrated circuit U 2, and connected to pin 11 and pin 1 of the U 3, the semiconductor integrated circuit U capacitor to the second pin 12, 15, 14 of the C 3, resistor R 10 , Diode D 5 is connected, and pin 10 of the copper circuit (U 2 ) is connected to pin 8 and pin 1 of the semiconductor integrated circuit (U 3 ) (U 4 ), pin 10 of the copper circuit (U 3 ) is a resistor R 12 , R 15 , transistor Q 1 , and diode D 7 were connected to the one-line heat failure lamp driving circuit. In addition, a resistor R 2 , a variable resistor R 4 , a capacitor C 2 , a resistor R 7 , R 8 , a diode D 3 , D 4 are connected between the terminal B and the pins 5 and 6 of the semiconductor integrated circuit U 1 . Connect pin 4 of the integrated circuit (U 1 ) to pins 5 and 2 of the semiconductor integrated circuits U 2 , U 3 , and the capacitor C 4 , resistor R 11 , diode to pins 4 , 1 , 2 of the semiconductor integrated circuit U 2 . D and 6 is connected to pin 6 of the same circuit (U 2) is a semiconductor integrated circuit (U 3) (U 4) pin 9 and the pin 3 and the semiconductor directly in connection to the pins 2 and the semiconductor integrated circuit (U 4) of the Pins 5 and 8 of circuit U 4 were connected, and pin 4 of circuit 4 (U 4 ) was connected to a phase-equivalent ramp drive circuit consisting of resistors R 13 , R 16 , transistor Q 2 , and diode D 8 .

또한, 반도체 직접회로 U3이 핀 3와 핀 5사이에 저항 R9, 콘덴서 C5를 연결하는 한편, 핀 4는 반도체 직접회로(U3)(U4)의 핀 13, 핀 6에 연결하며, 동 회로(U3)의 핀 11은 반도체 직접회로(U4)의 핀 9에 연결하고 동 회로(U3)의 핀 10은 저항 R14, R17, 트랜지스터 Q3, 다이오드 D9로 구성된 위상다름 램프구동회로와 연결 구성되어 있다.In addition, semiconductor integrated circuit U 3 connects resistor R 9 and capacitor C 5 between pins 3 and 5 , while pin 4 connects to pins 13 and 6 of semiconductor integrated circuit U 3 and U 4 . , copper pins 11 of the circuit (U 3) is connected to pin 9 of a semiconductor integrated circuit (U 4) and copper pins 10 of the circuit (U 3) is composed of resistors R 14, R 17, transistor Q 3, diode D 9 It is connected to the phase difference lamp driving circuit.

이와같은 본 회로의 작용 및 효과에 대하여 상세히 설명하면 다음과 같다.The operation and effects of the present circuit will be described in detail as follows.

지상기기 접지선과 측정기 접지장치와 연결하고 측정기 회로 동작 전원(SW)을 ON 시킨다.Connect the grounding device ground wire and the instrument grounding device and turn on the instrument circuit operating power (SW).

측정코자 하는 양측전원(절분점)인 SF6가스절연부자 개폐기 접속재 BIP 검전포인트에 측정기의 A, B단자를 접속한다. 즉, A, B 두 단자로부터 유입되는 유기전압 즉, AC전압의 신호가 입력되면 저항 R1과 R3, 혹은 저항 R2와 R4에 의해 내부회로에서 측정가능한 레벨로 감쇄되어 간다.Connect the A and B terminals of the instrument to the SF 6 gas insulated switchgear connector BIP inspection point, which is the power supply (cut point) on both sides. That is, when a signal of an induced voltage, ie, an AC voltage, flowing from two terminals A and B is inputted, the resistors R 1 and R 3 , or resistors R 2 and R 4 , are attenuated to a level measurable in the internal circuit.

즉, A 단자로 들어오는 전압을 V1이라 할때 C지점에서의 전압 VC와 B 지점으로 들어오는 전압을 V2할때 D지점에서의 전압 VD는

Figure kpo00001
가 되며, 이때 R1과 R2는 메가오옴단위의 큰 저항이며, R3와 R4는 수십킬로오옴의 가변저항이다.That is, when as the voltage entering the A terminal voltage V 1 V D at the point D when a second voltage entering the voltage V C and the B point in the point V is C
Figure kpo00001
Where R 1 and R 2 are large resistances in mega-ohms, and R 3 and R 4 are variable resistances in the tens of kiloohms.

A,B 두 단자로 부터 입력된 특고압의 유기전압이 R1과 R3, R2와 R4에 의해 레벨이 조정된 다음 회로의 다음단인 R5, R6, D1, D2혹은 R7, R8, D3, D4로 구성되는 레벨시프트(Level-Shift)에 가해져 AC신호가 접지레벨(Ground)로 이동된다.The induced high voltages from the A and B terminals are adjusted by R 1 and R 3 , R 2 and R 4 , and then R 5 , R 6 , D 1 , D 2 or The AC signal is moved to the ground level in response to a level shift made of R 7 , R 8 , D 3 , and D 4 .

Figure kpo00002
Figure kpo00002

레벨이동된 유기전압의 AC신호가 반도체 직접회로 소자인 U1에 의해 U1의 출력이 다음과 같이 구형파로 변환되어 진다.Is the AC signal of the level shift the output of the induced voltage U 1 U 1 by the semiconductor integrated circuit device is converted to a square wave, as follows.

Figure kpo00003
Figure kpo00003

U2는 U1의 하강지점(falling-edge)에서 신호의 유무를 검출하므로 U1의 출력이 아래와 같이 U2의 입력에 가해지면 U2의 출력은 로직상태가 ＂H＂가 되고 U1의 신호가 없으면 로직상태가 ＂L＂가 된다.U 2 is the output of the is applied to the input of U 2 as the output of the U 1 so detecting the presence or absence of the signal at the falling point (falling-edge) of the U 1 below U 2 is the logic state to be a "H" of the U 1 If no signal is present, the logic state is ＂L＂.

* U1의 출력신호가 있는 경우* When there is an output signal of U 1

U1의 출력

Figure kpo00004
Output of U 1
Figure kpo00004

U2의 출력

Figure kpo00005
Output of U 2
Figure kpo00005

* U1의 출력신호가 없는 경우* When there is no output signal of U 1

U1의 출력

Figure kpo00006
Output of U 1
Figure kpo00006

U2의 출력

Figure kpo00007
Output of U 2
Figure kpo00007

그 다음 U3에서는 A,B 두 지점으로부터 입력된 신호의 위상차를 비교하게 되는데 U3의 출력단(Pin3번)의 저항 R9와 콘덴서 C5는 미세한 위상차를 무시하기 위하여 구성된 로우패스휠터(Low-Passfilter)이다.Next, U 3 compares the phase difference between the signals inputted from two points A and B. The resistor R 9 and the capacitor C 5 of the output terminal (Pin 3 ) of U 3 are configured to ignore a small phase difference. Passfilter).

* 위상차에 관한 구체적인 설명* Specific explanation on phase difference

1) A,B 두 단자간 120°의 위상차가 생겼을때1) When a phase difference of 120 ° occurs between A and B terminals

Figure kpo00008
Figure kpo00008

즉, 위상차가 120°차이가 났을경우 U3의 Pin3 출력이 ＂H＂가 되므로 U3의 입력이 서로 다르다고 판정함.That is, the phase difference is determined so that the output of the Pin3 U 3 "H" when the wake 120 ° difference between the different type of U 3 each other.

2) A,B 두 단자간 240°의 위상차가 생겼을때2) When a phase difference of 240 ° occurs between A and B terminals

Figure kpo00009
Figure kpo00009

240°의 위상차가 났을 경우에도 서로 다른 상으로 판별한다.Different phases are distinguished even when the phase difference of 240 degrees occurs.

3) A,B 두 단자간 미세한 위상차가 생겼을 경우3) In case of small phase difference between A and B terminals

Figure kpo00010
Figure kpo00010

60°이하의 미세한 우상차는 로직 ＂L＂ 상태가 되므로 U3의 입력은 서로 같다고 판별하게 된다.Since the minute right difference of less than 60 ° becomes the logic ＂L＂ state, it is determined that the inputs of U 3 are the same.

U2의 C3, R10과 C4, C11은 A,B 두 지점간의 신호 유무에 따른 동작시간을 결정해 주는 역할을 한다.C 3 , R 10 and C 4 , C 11 of U 2 determine the operation time according to the presence or absence of signal between A and B points.

A,B 두 단자간에 발생되는 특고압의 유기전압을 60Hz의 주파수를 갖는 AC 신호이므로 이 유기전압의 주기 T는 16.7ms가 된다.

Figure kpo00011
The period T of the induced voltage becomes 16.7 ms because the induced high voltage of the high voltage generated between the two terminals A and B is an AC signal having a frequency of 60 Hz.
Figure kpo00011

즉, U2의 동작시간을 결정해 주는 시간 τ(타워)는 각각 τ1=C3×R10, τ2=C4×R11로 결정되므로 τ〉T이면 유기전압 신호의 입력되는 첫번째 하강지점(Falling edge)에서 U2의 출력이 동작하게 된다.That is, the time τ (tower) that determines the operating time of U 2 is determined as τ 1 = C 3 × R 10 and τ 2 = C 4 × R 11 , respectively, so if τ> T, the first falling input of the induced voltage signal is performed. At the falling edge, the output of U 2 is activated.

Figure kpo00012
Figure kpo00012

다음은 제1도의 전체 회로도에서 상판별을 위한 각각의 경우의 타이밍 그래프이다.The following is a timing graph in each case for the top discrimination in the overall circuit diagram of FIG.

1) 한쪽 단자 측정 접촉상태 불량시(측정기 리드선 단선및 접촉이 안된경우) :1) In case of poor contact status of one terminal measuring instrument

Figure kpo00013
Figure kpo00013

2) A,B 단자간 동상(同相)일 경우2) In case of A and B terminal in phase

Figure kpo00014
Figure kpo00014

3) A,B 단자간 相이 서로 다른 경우(異相) : 120°위상차 발생시3) When the phases of A and B terminals are different: When the phase difference occurs 120 °

Figure kpo00015
Figure kpo00015

본 측정기는 SF 가스 절연부하 개폐기의 BIP 검전포인트와 지상포인트와 지상변압기 Voltage Test Point에 유기되는 전압 및 위상차를 동시에 비교 검출하여 同相(Im phase)과 異相(Out of phase)을 판별하는 기능을 가지고 있으며 회로동작 전원 SW 조작의 다른 operator(조작장치)가 없으므로 사용이 극히 간단하고 전압 3ø 380V 이하의 전압에는 충전부위 직접상측정이 가능하다. 따라서 무정전으로 인한 공급신뢰도 향상과 전력판매 이득의 효과, 안전사고 예방, 측정작업인원 및 시간절약등 다수의 효과가 기대되는 유익한 발명이다.This instrument has the function of discriminating the phase and out of phase by comparing and detecting the voltage and phase difference induced at the BIP inspection point and ground point and ground transformer voltage test point of SF gas insulated load switch. In addition, since there is no other operator of circuit operation power SW operation, it is very simple to use and direct phase measurement of charging part is possible at voltage below 3ø380V. Therefore, it is an advantageous invention that a number of effects are expected such as the improvement of supply reliability and the benefits of power sales due to the uninterrupted power, the prevention of safety accidents, the measurement workforce and the time saving.

Claims (1)

A,B 단자와 반도체 직접회로(U1)의 핀 1,2,5,6 사이에 저항 R1, R2, R5-R8, 가변저항 R3, R4, 콘덴서 C1, C2, 다이오드 D1, D4를 연결하고, 핀 3,4를 콘덴서 C3, C4, 저항 R10, R11, 다이오드 D5, D6로 구성된 반도체 직접회로(U2)의 핀 11,5와 연결하는 한편, 반도체 직접회로(U3)의 핀 3와 5 사이에 저항 R9, 콘덴서 C5를 연결하고, 반도체 직접회로(U3)(U4)를 통해 램프구성 회로와 연결한 것을 특징으로 하는 특고압 지중배전 선로용 상판별기.Resistor R 1 , R 2 , R 5 -R 8 , Variable resistor R 3 , R 4 , Capacitor C 1 , C 2 between A, B terminal and pins 1,2 , 5 , 6 of semiconductor integrated circuit (U 1 ) , Pins 11,5 of the semiconductor integrated circuit (U 2 ) consisting of the diodes D 1 , D 4 , and the pins 3 , 4 consisting of capacitors C 3 , C 4 , resistors R 10 , R 11 , diodes D 5 , D 6 . connecting the other hand, that the semiconductor connecting the resistor R 9, capacitor C 5, between pins 3 and 5 of the integrated circuit (U 3), and through a semiconductor integrated circuit (U 3) (U 4) connected to the lamp circuit arrangement An upper plate separator for the special high voltage underground power distribution line.
KR1019880010477A 1988-08-17 1988-08-17 Wire phase detector of super high earth wire KR910005700B1 (en)

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Application Number Priority Date Filing Date Title
KR1019880010477A KR910005700B1 (en) 1988-08-17 1988-08-17 Wire phase detector of super high earth wire

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Application Number Priority Date Filing Date Title
KR1019880010477A KR910005700B1 (en) 1988-08-17 1988-08-17 Wire phase detector of super high earth wire

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KR900003637A KR900003637A (en) 1990-03-26
KR910005700B1 true KR910005700B1 (en) 1991-08-02

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