KR910005476A - Manufacturing Method of NPN Transistor for Horizontal Operation - Google Patents

Manufacturing Method of NPN Transistor for Horizontal Operation Download PDF

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Publication number
KR910005476A
KR910005476A KR1019890012018A KR890012018A KR910005476A KR 910005476 A KR910005476 A KR 910005476A KR 1019890012018 A KR1019890012018 A KR 1019890012018A KR 890012018 A KR890012018 A KR 890012018A KR 910005476 A KR910005476 A KR 910005476A
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South Korea
Prior art keywords
groove
oxide film
polycrystalline silicon
silicon
manufacturing
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KR1019890012018A
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Korean (ko)
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KR0144353B1 (en
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류시봉
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문정환
금성일렉트론 주식회사
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Priority to KR1019890012018A priority Critical patent/KR0144353B1/en
Publication of KR910005476A publication Critical patent/KR910005476A/en
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Publication of KR0144353B1 publication Critical patent/KR0144353B1/en

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  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

내용 없음No content

Description

수평 동작용 NPN 트랜지스터의 제조방법Manufacturing Method of NPN Transistor for Horizontal Operation

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 제조공정도,1 is a manufacturing process diagram of the present invention,

제2도는 본 발명의 트랜지스터 평면도.2 is a plan view of a transistor of the present invention.

Claims (1)

N형 기판(1)에 매몰 산화막(2)을 형성한 후 그 위에 산화막(3)을 성장시키고, 이방성 홈 식각법을 이용하여 실리콘(5)을 식각하여 이 홈 식각부(4)에 P형 다결정 실리콘(6)을 채운 후 P형 불순물 확산 및 표면 산화막을 형성하며, 에미터와 콜렉터가 형성될 부분의 마스킹 작업을 하고 홈식각하여 홈식각부(8) 형성후 N+다결정 실리콘(7)을 채우고 표면을 평탄화시킨 다음 열처리하여 실리콘과 전술한 베이스 영역(6a)에 불순물이 확산되게 하므로 전자는 콜렉터, 후자는 에미터 영역으로 이용가능하게 하고 산화막을 성장시키고, 마스크로 격리용 홈 식각 모양을 형성하고 열산화시킨 후 유전체나 P+다결정 실리콘을 채우고 표면을 평탄화 시키며, 다결정 실리콘 위에 전극용 콘택트(6b) (7a) (7b)를 형성하고 전도성 금속으로 도포함을 특징으로하는 수평 동작용 NPN 트랜지스터의 제조방법.After the buried oxide film 2 is formed on the N-type substrate 1, the oxide film 3 is grown thereon, and the silicon 5 is etched using the anisotropic groove etching method to form the P-type groove 4 in the groove etched portion 4. After filling the polycrystalline silicon (6) to form a P-type impurity diffusion and surface oxide film, masking the portion where the emitter and collector will be formed, and etching the groove to form the groove etching portion (8) after N + polycrystalline silicon (7) And the surface are planarized and then thermally treated to allow impurities to diffuse in the silicon and the base region 6a described above, making the former available as a collector and the latter as an emitter region, growing an oxide film, and forming a groove etch for isolation with a mask. After forming and thermally oxidizing, fill the dielectric or P + polycrystalline silicon and planarize the surface, and form a contact for the electrode (6b) (7a) (7b) on the polycrystalline silicon, and for horizontal operation characterized by coating with a conductive metal NP Method of manufacturing N transistors. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890012018A 1989-08-23 1989-08-23 Method of manufacturing bipolar device KR0144353B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890012018A KR0144353B1 (en) 1989-08-23 1989-08-23 Method of manufacturing bipolar device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890012018A KR0144353B1 (en) 1989-08-23 1989-08-23 Method of manufacturing bipolar device

Publications (2)

Publication Number Publication Date
KR910005476A true KR910005476A (en) 1991-03-30
KR0144353B1 KR0144353B1 (en) 1998-07-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890012018A KR0144353B1 (en) 1989-08-23 1989-08-23 Method of manufacturing bipolar device

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Publication number Publication date
KR0144353B1 (en) 1998-07-01

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